Merge branch '4.0-fixes' into mips-for-linux-next
[cascardo/linux.git] / arch / mips / include / asm / cpu.h
index e492c74..e3adca1 100644 (file)
@@ -67,7 +67,7 @@
 #define PRID_IMP_R4300         0x0b00
 #define PRID_IMP_VR41XX                0x0c00
 #define PRID_IMP_R12000                0x0e00
-#define PRID_IMP_R14000                0x0f00
+#define PRID_IMP_R14000                0x0f00          /* R14K && R16K */
 #define PRID_IMP_R8000         0x1000
 #define PRID_IMP_PR4450                0x1200
 #define PRID_IMP_R4600         0x2000
@@ -284,8 +284,8 @@ enum cpu_type_enum {
        CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
        CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
        CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
-       CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
-       CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+       CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
+       CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
        CPU_SR71000, CPU_TX49XX,
 
        /*
@@ -378,6 +378,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_FRE           0x800000000ull /* FRE & UFE bits implemented */
 #define MIPS_CPU_RW_LLB                0x1000000000ull /* LLADDR/LLB writes are allowed */
 #define MIPS_CPU_XPA           0x2000000000ull /* CPU supports Extended Physical Addressing */
+#define MIPS_CPU_CDMM          0x4000000000ull /* CPU has Common Device Memory Map */
 
 /*
  * CPU ASE encodings