/* On older ones it's unavailable */
return -1;
- /* CPUs which do not require the workaround */
- case CPU_P5600:
- case CPU_I6400:
- return 0;
-
default:
- WARN_ONCE(1, "pm-cps: FSB flush unsupported for this CPU\n");
- return -1;
+ /* Assume that the CPU does not need this workaround */
+ return 0;
}
/*
i * line_size * line_stride, t0);
}
- /* Completion barrier */
+ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(pp, stype_memory);
uasm_i_ehb(pp);
uasm_il_beqz(&p, &r, t2, lbl_incready);
uasm_i_addiu(&p, t1, t1, 1);
- /* Ordering barrier */
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
/*
cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
Index_Writeback_Inv_D, lbl_flushdcache);
- /* Completion barrier */
+ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
- /* Sync to ensure previous interventions are complete */
+ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_intervention);
uasm_i_ehb(&p);
goto gen_done;
}
- /* Completion barrier */
+ /* Barrier to ensure write to CPC command is complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
}
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
- /* Completion barrier */
+ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
uasm_il_beqz(&p, &r, t2, lbl_decready);
uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
- /* Ordering barrier */
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
}
*/
uasm_build_label(&l, p, lbl_secondary_cont);
- /* Ordering barrier */
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
}