MIPS: pm-cps: Remove selection of sync types

[cascardo/linux.git] / arch / mips / kernel / pm-cps.c

diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 5b31a94..b3a7d36 100644 (file)
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -73,11 +73,6 @@ DEFINE_PER_CPU_ALIGNED(struct mips_static_suspend_state, cps_cpu_state);
 static struct uasm_label labels[32] __initdata;
 static struct uasm_reloc relocs[32] __initdata;
 
-/* CPU dependant sync types */
-static unsigned stype_intervention;
-static unsigned stype_memory;
-static unsigned stype_ordering;
-
 enum mips_reg {
        zero, at, v0, v1, a0, a1, a2, a3,
        t0, t1, t2, t3, t4, t5, t6, t7,
@@ -272,14 +267,9 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
                /* On older ones it's unavailable */
                return -1;
 
-       /* CPUs which do not require the workaround */
-       case CPU_P5600:
-       case CPU_I6400:
-               return 0;
-
        default:
-               WARN_ONCE(1, "pm-cps: FSB flush unsupported for this CPU\n");
-               return -1;
+               /* Assume that the CPU does not need this workaround */
+               return 0;
        }
 
        /*
@@ -320,8 +310,8 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
                             i * line_size * line_stride, t0);
        }
 
-       /* Completion barrier */
-       uasm_i_sync(pp, stype_memory);
+       /* Barrier ensuring previous cache invalidates are complete */
+       uasm_i_sync(pp, STYPE_SYNC);
        uasm_i_ehb(pp);
 
        /* Check whether the pipeline stalled due to the FSB being full */
@@ -411,7 +401,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
 
        if (coupled_coherence) {
                /* Increment ready_count */
-               uasm_i_sync(&p, stype_ordering);
+               uasm_i_sync(&p, STYPE_SYNC_MB);
                uasm_build_label(&l, p, lbl_incready);
                uasm_i_ll(&p, t1, 0, r_nc_count);
                uasm_i_addiu(&p, t2, t1, 1);
@@ -419,8 +409,8 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
                uasm_il_beqz(&p, &r, t2, lbl_incready);
                uasm_i_addiu(&p, t1, t1, 1);
 
-               /* Ordering barrier */
-               uasm_i_sync(&p, stype_ordering);
+               /* Barrier ensuring all CPUs see the updated r_nc_count value */
+               uasm_i_sync(&p, STYPE_SYNC_MB);
 
                /*
                 * If this is the last VPE to become ready for non-coherence
@@ -472,8 +462,8 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
        cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
                              Index_Writeback_Inv_D, lbl_flushdcache);
 
-       /* Completion barrier */
-       uasm_i_sync(&p, stype_memory);
+       /* Barrier ensuring previous cache invalidates are complete */
+       uasm_i_sync(&p, STYPE_SYNC);
        uasm_i_ehb(&p);
 
        /*
@@ -485,8 +475,8 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
        uasm_i_sw(&p, t0, 0, r_pcohctl);
        uasm_i_lw(&p, t0, 0, r_pcohctl);
 
-       /* Sync to ensure previous interventions are complete */
-       uasm_i_sync(&p, stype_intervention);
+       /* Barrier to ensure write to coherence control is complete */
+       uasm_i_sync(&p, STYPE_SYNC);
        uasm_i_ehb(&p);
 
        /* Disable coherence */
@@ -531,8 +521,8 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
                        goto gen_done;
                }
 
-               /* Completion barrier */
-               uasm_i_sync(&p, stype_memory);
+               /* Barrier to ensure write to CPC command is complete */
+               uasm_i_sync(&p, STYPE_SYNC);
                uasm_i_ehb(&p);
        }
 
@@ -566,22 +556,22 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
        uasm_i_sw(&p, t0, 0, r_pcohctl);
        uasm_i_lw(&p, t0, 0, r_pcohctl);
 
-       /* Completion barrier */
-       uasm_i_sync(&p, stype_memory);
+       /* Barrier to ensure write to coherence control is complete */
+       uasm_i_sync(&p, STYPE_SYNC);
        uasm_i_ehb(&p);
 
        if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {
                /* Decrement ready_count */
                uasm_build_label(&l, p, lbl_decready);
-               uasm_i_sync(&p, stype_ordering);
+               uasm_i_sync(&p, STYPE_SYNC_MB);
                uasm_i_ll(&p, t1, 0, r_nc_count);
                uasm_i_addiu(&p, t2, t1, -1);
                uasm_i_sc(&p, t2, 0, r_nc_count);
                uasm_il_beqz(&p, &r, t2, lbl_decready);
                uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
 
-               /* Ordering barrier */
-               uasm_i_sync(&p, stype_ordering);
+               /* Barrier ensuring all CPUs see the updated r_nc_count value */
+               uasm_i_sync(&p, STYPE_SYNC_MB);
        }
 
        if (coupled_coherence && (state == CPS_PM_CLOCK_GATED)) {
@@ -602,8 +592,8 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
                 */
                uasm_build_label(&l, p, lbl_secondary_cont);
 
-               /* Ordering barrier */
-               uasm_i_sync(&p, stype_ordering);
+               /* Barrier ensuring all CPUs see the updated r_nc_count value */
+               uasm_i_sync(&p, STYPE_SYNC_MB);
        }
 
        /* The core is coherent, time to return to C code */
@@ -673,22 +663,6 @@ static int __init cps_pm_init(void)
        unsigned cpu;
        int err;
 
-       /* Detect appropriate sync types for the system */
-       switch (current_cpu_data.cputype) {
-       case CPU_INTERAPTIV:
-       case CPU_PROAPTIV:
-       case CPU_M5150:
-       case CPU_P5600:
-       case CPU_I6400:
-               stype_intervention = 0x2;
-               stype_memory = 0x3;
-               stype_ordering = 0x10;
-               break;
-
-       default:
-               pr_warn("Power management is using heavyweight sync 0\n");
-       }
-
        /* A CM is required for all non-coherent states */
        if (!mips_cm_present()) {
                pr_warn("pm-cps: no CM, non-coherent states unavailable\n");