tree-wide: replace config_enabled() with IS_ENABLED()

[cascardo/linux.git] / arch / mips / math-emu / cp1emu.c

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 99977c3..92d15e6 100644 (file)
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -445,9 +445,11 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
        case spec_op:
                switch (insn.r_format.func) {
                case jalr_op:
-                       regs->regs[insn.r_format.rd] =
-                               regs->cp0_epc + dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                       if (insn.r_format.rd != 0) {
+                               regs->regs[insn.r_format.rd] =
+                                       regs->cp0_epc + dec_insn.pc_inc +
+                                       dec_insn.next_pc_inc;
+                       }
                        /* Fall through */
                case jr_op:
                        /* For R6, JR already emulated in jalr_op */
@@ -625,8 +627,8 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                                dec_insn.pc_inc +
                                dec_insn.next_pc_inc;
                return 1;
-       case cbcond0_op:
-       case cbcond1_op:
+       case pop10_op:
+       case pop30_op:
                if (!cpu_has_mips_r6)
                        break;
                if (insn.i_format.rt && !insn.i_format.rs)
@@ -681,14 +683,14 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                        dec_insn.next_pc_inc;
 
                return 1;
-       case beqzcjic_op:
+       case pop66_op:
                if (!cpu_has_mips_r6)
                        break;
                *contpc = regs->cp0_epc + dec_insn.pc_inc +
                        dec_insn.next_pc_inc;
 
                return 1;
-       case bnezcjialc_op:
+       case pop76_op:
                if (!cpu_has_mips_r6)
                        break;
                if (!insn.i_format.rs)
@@ -782,10 +784,10 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
  */
 static inline int cop1_64bit(struct pt_regs *xcp)
 {
-       if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
+       if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
                return 1;
-       else if (config_enabled(CONFIG_32BIT) &&
-                !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
+       else if (IS_ENABLED(CONFIG_32BIT) &&
+                !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
                return 0;
 
        return !test_thread_flag(TIF_32BIT_FPREGS);
@@ -1675,7 +1677,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                        union ieee754sp(*b) (union ieee754sp, union ieee754sp);
                        union ieee754sp(*u) (union ieee754sp);
                } handler;
-               union ieee754sp fs, ft;
+               union ieee754sp fd, fs, ft;
 
                switch (MIPSInst_FUNC(ir)) {
                        /* binary ops */
@@ -1946,6 +1948,17 @@ copcsr:
                        rfmt = w_fmt;
                        goto copcsr;
 
+               case fsel_op:
+                       if (!cpu_has_mips_r6)
+                               return SIGILL;
+
+                       SPFROMREG(fd, MIPSInst_FD(ir));
+                       if (fd.bits & 0x1)
+                               SPFROMREG(rv.s, MIPSInst_FT(ir));
+                       else
+                               SPFROMREG(rv.s, MIPSInst_FS(ir));
+                       break;
+
                case fcvtl_op:
                        if (!cpu_has_mips_3_4_5_64_r2_r6)
                                return SIGILL;
@@ -1994,7 +2007,7 @@ copcsr:
        }
 
        case d_fmt: {
-               union ieee754dp fs, ft;
+               union ieee754dp fd, fs, ft;
                union {
                        union ieee754dp(*b) (union ieee754dp, union ieee754dp);
                        union ieee754dp(*u) (union ieee754dp);
@@ -2244,6 +2257,17 @@ dcopuop:
                        rfmt = w_fmt;
                        goto copcsr;
 
+               case fsel_op:
+                       if (!cpu_has_mips_r6)
+                               return SIGILL;
+
+                       DPFROMREG(fd, MIPSInst_FD(ir));
+                       if (fd.bits & 0x1)
+                               DPFROMREG(rv.d, MIPSInst_FT(ir));
+                       else
+                               DPFROMREG(rv.d, MIPSInst_FS(ir));
+                       break;
+
                case fcvtl_op:
                        if (!cpu_has_mips_3_4_5_64_r2_r6)
                                return SIGILL;