MIPS: Pistachio: Enable KASLR

[cascardo/linux.git] / arch / mips / pistachio / init.c

diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c
index 96ba2cc..ab79828 100644 (file)
--- a/arch/mips/pistachio/init.c
+++ b/arch/mips/pistachio/init.c
@@ -2,6 +2,7 @@
  * Pistachio platform setup
  *
  * Copyright (C) 2014 Google, Inc.
+ * Copyright (C) 2016 Imagination Technologies
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -9,6 +10,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
@@ -24,9 +26,38 @@
 #include <asm/smp-ops.h>
 #include <asm/traps.h>
 
+/*
+ * Core revision register decoding
+ * Bits 23 to 20: Major rev
+ * Bits 15 to 8: Minor rev
+ * Bits 7 to 0: Maintenance rev
+ */
+#define PISTACHIO_CORE_REV_REG 0xB81483D0
+#define PISTACHIO_CORE_REV_A1  0x00100006
+#define PISTACHIO_CORE_REV_B0  0x00100106
+
 const char *get_system_type(void)
 {
-       return "IMG Pistachio SoC";
+       u32 core_rev;
+       const char *sys_type;
+
+       core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
+
+       switch (core_rev) {
+       case PISTACHIO_CORE_REV_B0:
+               sys_type = "IMG Pistachio SoC (B0)";
+               break;
+
+       case PISTACHIO_CORE_REV_A1:
+               sys_type = "IMG Pistachio SoC (A1)";
+               break;
+
+       default:
+               sys_type = "IMG Pistachio SoC";
+               break;
+       }
+
+       return sys_type;
 }
 
 static void __init plat_setup_iocoherency(void)
@@ -52,12 +83,16 @@ static void __init plat_setup_iocoherency(void)
        }
 }
 
-void __init plat_mem_setup(void)
+void __init *plat_get_fdt(void)
 {
        if (fw_arg0 != -2)
                panic("Device-tree not present");
+       return (void *)fw_arg1;
+}
 
-       __dt_setup_arch((void *)fw_arg1);
+void __init plat_mem_setup(void)
+{
+       __dt_setup_arch(plat_get_fdt());
 
        plat_setup_iocoherency();
 }
@@ -109,6 +144,8 @@ void __init prom_init(void)
        mips_cm_probe();
        mips_cpc_probe();
        register_cps_smp_ops();
+
+       pr_info("SoC Type: %s\n", get_system_type());
 }
 
 void __init prom_free_prom_memory(void)