Merge tag 'omap-for-v4.8/dt-part1-signed-v2' of git://git.kernel.org/pub/scm/linux...

[cascardo/linux.git] / arch / parisc / kernel / time.c

diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c
index 400acac..31ec99a 100644 (file)
--- a/arch/parisc/kernel/time.c
+++ b/arch/parisc/kernel/time.c
@@ -38,6 +38,18 @@
 
 static unsigned long clocktick __read_mostly;  /* timer cycles per tick */
 
+#ifndef CONFIG_64BIT
+/*
+ * The processor-internal cycle counter (Control Register 16) is used as time
+ * source for the sched_clock() function.  This register is 64bit wide on a
+ * 64-bit kernel and 32bit on a 32-bit kernel. Since sched_clock() always
+ * requires a 64bit counter we emulate on the 32-bit kernel the higher 32bits
+ * with a per-cpu variable which we increase every time the counter
+ * wraps-around (which happens every ~4 secounds).
+ */
+static DEFINE_PER_CPU(unsigned long, cr16_high_32_bits);
+#endif
+
 /*
  * We keep time on PA-RISC Linux by using the Interval Timer which is
  * a pair of registers; one is read-only and one is write-only; both
@@ -108,6 +120,12 @@ irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
         */
        mtctl(next_tick, 16);
 
+#if !defined(CONFIG_64BIT)
+       /* check for overflow on a 32bit kernel (every ~4 seconds). */
+       if (unlikely(next_tick < now))
+               this_cpu_inc(cr16_high_32_bits);
+#endif
+
        /* Skip one clocktick on purpose if we missed next_tick.
         * The new CR16 must be "later" than current CR16 otherwise
         * itimer would not fire until CR16 wrapped - e.g 4 seconds
@@ -219,6 +237,12 @@ void __init start_cpu_itimer(void)
        unsigned int cpu = smp_processor_id();
        unsigned long next_tick = mfctl(16) + clocktick;
 
+#if defined(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK) && defined(CONFIG_64BIT)
+       /* With multiple 64bit CPUs online, the cr16's are not syncronized. */
+       if (cpu != 0)
+               clear_sched_clock_stable();
+#endif
+
        mtctl(next_tick, 16);           /* kick off Interval Timer (CR16) */
 
        per_cpu(cpu_data, cpu).it_value = next_tick;
@@ -246,15 +270,47 @@ void read_persistent_clock(struct timespec *ts)
        }
 }
 
+
+/*
+ * sched_clock() framework
+ */
+
+static u32 cyc2ns_mul __read_mostly;
+static u32 cyc2ns_shift __read_mostly;
+
+u64 sched_clock(void)
+{
+       u64 now;
+
+       /* Get current cycle counter (Control Register 16). */
+#ifdef CONFIG_64BIT
+       now = mfctl(16);
+#else
+       now = mfctl(16) + (((u64) this_cpu_read(cr16_high_32_bits)) << 32);
+#endif
+
+       /* return the value in ns (cycles_2_ns) */
+       return mul_u64_u32_shr(now, cyc2ns_mul, cyc2ns_shift);
+}
+
+
+/*
+ * timer interrupt and sched_clock() initialization
+ */
+
 void __init time_init(void)
 {
        unsigned long current_cr16_khz;
 
+       current_cr16_khz = PAGE0->mem_10msec/10;  /* kHz */
        clocktick = (100 * PAGE0->mem_10msec) / HZ;
 
+       /* calculate mult/shift values for cr16 */
+       clocks_calc_mult_shift(&cyc2ns_mul, &cyc2ns_shift, current_cr16_khz,
+                               NSEC_PER_MSEC, 0);
+
        start_cpu_itimer();     /* get CPU 0 started */
 
        /* register at clocksource framework */
-       current_cr16_khz = PAGE0->mem_10msec/10;  /* kHz */
        clocksource_register_khz(&clocksource_cr16, current_cr16_khz);
 }