powerpc/powernv: Use PE instead of number during setup and release

[cascardo/linux.git] / arch / powerpc / platforms / powernv / pci.h

diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 3f814f3..904f60b 100644 (file)
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -53,14 +53,7 @@ struct pnv_ioda_pe {
        /* PE number */
        unsigned int            pe_number;
 
-       /* "Weight" assigned to the PE for the sake of DMA resource
-        * allocations
-        */
-       unsigned int            dma_weight;
-
        /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
-       int                     tce32_seg;
-       int                     tce32_segcount;
        struct iommu_table_group table_group;
 
        /* 64-bit TCE bypass region */
@@ -78,7 +71,6 @@ struct pnv_ioda_pe {
        struct list_head        slaves;
 
        /* Link in list of PE#s */
-       struct list_head        dma_link;
        struct list_head        list;
 };
 
@@ -110,19 +102,18 @@ struct pnv_phb {
                         unsigned int is_64, struct msi_msg *msg);
        void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
        void (*fixup_phb)(struct pci_controller *hose);
-       u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
        int (*init_m64)(struct pnv_phb *phb);
        void (*reserve_m64_pe)(struct pci_bus *bus,
                               unsigned long *pe_bitmap, bool all);
-       int (*pick_m64_pe)(struct pci_bus *bus, bool all);
+       struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
        int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
        void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
        int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
 
        struct {
                /* Global bridge info */
-               unsigned int            total_pe;
-               unsigned int            reserved_pe;
+               unsigned int            total_pe_num;
+               unsigned int            reserved_pe_idx;
 
                /* 32-bit MMIO window */
                unsigned int            m32_size;
@@ -141,15 +132,19 @@ struct pnv_phb {
                unsigned int            io_segsize;
                unsigned int            io_pci_base;
 
-               /* PE allocation bitmap */
-               unsigned long           *pe_alloc;
-               /* PE allocation mutex */
+               /* PE allocation */
                struct mutex            pe_alloc_mutex;
+               unsigned long           *pe_alloc;
+               struct pnv_ioda_pe      *pe_array;
 
                /* M32 & IO segment maps */
+               unsigned int            *m64_segmap;
                unsigned int            *m32_segmap;
                unsigned int            *io_segmap;
-               struct pnv_ioda_pe      *pe_array;
+
+               /* DMA32 segment maps - IODA1 only */
+               unsigned int            dma32_count;
+               unsigned int            *dma32_segmap;
 
                /* IRQ chip */
                int                     irq_chip_init;
@@ -167,20 +162,6 @@ struct pnv_phb {
                 */
                unsigned char           pe_rmap[0x10000];
 
-               /* 32-bit TCE tables allocation */
-               unsigned long           tce32_count;
-
-               /* Total "weight" for the sake of DMA resources
-                * allocation
-                */
-               unsigned int            dma_weight;
-               unsigned int            dma_pe_count;
-
-               /* Sorted list of used PE's, sorted at
-                * boot for resource allocation purposes
-                */
-               struct list_head        pe_dma_list;
-
                /* TCE cache invalidate registers (physical and
                 * remapped)
                 */