Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[cascardo/linux.git] / arch / x86 / kernel / cpu / amd.c

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 782c456..84bee67 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -518,10 +518,9 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 {
        u32 dummy;
-
-#ifdef CONFIG_SMP
        unsigned long long value;
 
+#ifdef CONFIG_SMP
        /*
         * Disable TLB flush filter by setting HWCR.FFDIS on K8
         * bit 6 of msr C001_0015
@@ -559,12 +558,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 * (AMD Erratum #110, docId: 25759).
                 */
                if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
-                       u64 val;
-
                        clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
-                       if (!rdmsrl_amd_safe(0xc001100d, &val)) {
-                               val &= ~(1ULL << 32);
-                               wrmsrl_amd_safe(0xc001100d, val);
+                       if (!rdmsrl_amd_safe(0xc001100d, &value)) {
+                               value &= ~(1ULL << 32);
+                               wrmsrl_amd_safe(0xc001100d, value);
                        }
                }
 
@@ -617,13 +614,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
        if ((c->x86 == 0x15) &&
            (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
            !cpu_has(c, X86_FEATURE_TOPOEXT)) {
-               u64 val;
 
-               if (!rdmsrl_safe(0xc0011005, &val)) {
-                       val |= 1ULL << 54;
-                       wrmsrl_safe(0xc0011005, val);
-                       rdmsrl(0xc0011005, val);
-                       if (val & (1ULL << 54)) {
+               if (!rdmsrl_safe(0xc0011005, &value)) {
+                       value |= 1ULL << 54;
+                       wrmsrl_safe(0xc0011005, value);
+                       rdmsrl(0xc0011005, value);
+                       if (value & (1ULL << 54)) {
                                set_cpu_cap(c, X86_FEATURE_TOPOEXT);
                                printk(KERN_INFO FW_INFO "CPU: Re-enabling "
                                  "disabled Topology Extensions Support\n");
@@ -637,11 +633,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         */
        if ((c->x86 == 0x15) &&
            (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
-               u64 val;
 
-               if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
-                       val |= 0x1E;
-                       wrmsrl_safe(0xc0011021, val);
+               if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
+                       value |= 0x1E;
+                       wrmsrl_safe(0xc0011021, value);
                }
        }
 
@@ -703,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
        if (c->x86 > 0x11)
                set_cpu_cap(c, X86_FEATURE_ARAT);
 
-       /*
-        * Disable GART TLB Walk Errors on Fam10h. We do this here
-        * because this is always needed when GART is enabled, even in a
-        * kernel which has no MCE support built in.
-        */
        if (c->x86 == 0x10) {
                /*
+                * Disable GART TLB Walk Errors on Fam10h. We do this here
+                * because this is always needed when GART is enabled, even in a
+                * kernel which has no MCE support built in.
                 * BIOS should disable GartTlbWlk Errors themself. If
                 * it doesn't do it here as suggested by the BKDG.
                 *
@@ -723,6 +716,21 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                        mask |= (1 << 10);
                        wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
                }
+
+               /*
+                * On family 10h BIOS may not have properly enabled WC+ support,
+                * causing it to be converted to CD memtype. This may result in
+                * performance degradation for certain nested-paging guests.
+                * Prevent this conversion by clearing bit 24 in
+                * MSR_AMD64_BU_CFG2.
+                *
+                * NOTE: we want to use the _safe accessors so as not to #GP kvm
+                * guests on older kvm hosts.
+                */
+
+               rdmsrl_safe(MSR_AMD64_BU_CFG2, &value);
+               value &= ~(1ULL << 24);
+               wrmsrl_safe(MSR_AMD64_BU_CFG2, value);
        }
 
        rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);