x86/AMD: Fix last level cache topology for AMD Fam17h systems

[cascardo/linux.git] / arch / x86 / kernel / cpu / amd.c

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4a70fc6..a8816b3 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -352,6 +352,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
        unsigned bits;
        int cpu = smp_processor_id();
+       unsigned int socket_id, core_complex_id;
 
        bits = c->x86_coreid_bits;
        /* Low order bits define the core id (index of core in socket) */
@@ -361,6 +362,18 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
        /* use socket ID also for last level cache */
        per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
        amd_get_topology(c);
+
+       /*
+        * Fix percpu cpu_llc_id here as LLC topology is different
+        * for Fam17h systems.
+        */
+        if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
+               return;
+
+       socket_id       = (c->apicid >> bits) - 1;
+       core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3;
+
+       per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
 #endif
 }