x86/platform/intel_mid_pci: Rework IRQ0 workaround

[cascardo/linux.git] / arch / x86 / pci / intel_mid_pci.c

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 8b93e63..ae97f24 100644 (file)
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -37,6 +37,7 @@
 
 /* Quirks for the listed devices */
 #define PCI_DEVICE_ID_INTEL_MRFL_MMC   0x1190
+#define PCI_DEVICE_ID_INTEL_MRFL_HSU   0x1191
 
 /* Fixed BAR fields */
 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00        /* Fixed BAR (TBD) */
@@ -224,14 +225,21 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 
                /* Special treatment for IRQ0 */
                if (dev->irq == 0) {
+                       /*
+                        * Skip HS UART common registers device since it has
+                        * IRQ0 assigned and not used by the kernel.
+                        */
+                       if (dev->device == PCI_DEVICE_ID_INTEL_MRFL_HSU)
+                               return -EBUSY;
                        /*
                         * TNG has IRQ0 assigned to eMMC controller. But there
                         * are also other devices with bogus PCI configuration
                         * that have IRQ0 assigned. This check ensures that
-                        * eMMC gets it.
+                        * eMMC gets it. The rest of devices still could be
+                        * enabled without interrupt line being allocated.
                         */
                        if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
-                               return -EBUSY;
+                               return 0;
                }
                break;
        default: