Merge branch 'for-3.17' of git://linux-nfs.org/~bfields/linux

[cascardo/linux.git] / drivers / clk / st / clkgen-pll.c

diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d4ef4f4..29769d7 100644 (file)
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -192,6 +192,42 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
        .ops            = &stm_pll3200c32_ops,
 };
 
+static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+       /* 407 C0 PLL0 */
+       .pdn_status     = CLKGEN_FIELD(0x2a0,   0x1,                    8),
+       .locked_status  = CLKGEN_FIELD(0x2a0,   0x1,                    24),
+       .ndiv           = CLKGEN_FIELD(0x2a4,   C32_NDIV_MASK,          16),
+       .idf            = CLKGEN_FIELD(0x2a4,   C32_IDF_MASK,           0x0),
+       .num_odfs = 1,
+       .odf            = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK,           0) },
+       .odf_gate       = { CLKGEN_FIELD(0x2b4, 0x1,                    6) },
+       .ops            = &stm_pll3200c32_ops,
+};
+
+static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+       /* 407 C0 PLL1 */
+       .pdn_status     = CLKGEN_FIELD(0x2c8,   0x1,                    8),
+       .locked_status  = CLKGEN_FIELD(0x2c8,   0x1,                    24),
+       .ndiv           = CLKGEN_FIELD(0x2cc,   C32_NDIV_MASK,          16),
+       .idf            = CLKGEN_FIELD(0x2cc,   C32_IDF_MASK,           0x0),
+       .num_odfs = 1,
+       .odf            = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK,           0) },
+       .odf_gate       = { CLKGEN_FIELD(0x2dc, 0x1,                    6) },
+       .ops            = &stm_pll3200c32_ops,
+};
+
+static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
+       /* 407 A9 */
+       .pdn_status     = CLKGEN_FIELD(0x1a8,   0x1,                    0),
+       .locked_status  = CLKGEN_FIELD(0x87c,   0x1,                    0),
+       .ndiv           = CLKGEN_FIELD(0x1b0,   C32_NDIV_MASK,          0),
+       .idf            = CLKGEN_FIELD(0x1a8,   C32_IDF_MASK,           25),
+       .num_odfs = 1,
+       .odf            = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK,           8) },
+       .odf_gate       = { CLKGEN_FIELD(0x1ac, 0x1,                    28) },
+       .ops            = &stm_pll3200c32_ops,
+};
+
 /**
  * DOC: Clock Generated by PLL, rate set and enabled by bootloader
  *
@@ -586,6 +622,18 @@ static struct of_device_id c32_pll_of_match[] = {
                .compatible = "st,stih407-plls-c32-a0",
                .data = &st_pll3200c32_407_a0,
        },
+       {
+               .compatible = "st,stih407-plls-c32-c0_0",
+               .data = &st_pll3200c32_407_c0_0,
+       },
+       {
+               .compatible = "st,stih407-plls-c32-c0_1",
+               .data = &st_pll3200c32_407_c0_1,
+       },
+       {
+               .compatible = "st,stih407-plls-c32-a9",
+               .data = &st_pll3200c32_407_a9,
+       },
        {}
 };