Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma

[cascardo/linux.git] / drivers / edac / i82860_edac.c

diff --git a/drivers/edac/i82860_edac.c b/drivers/edac/i82860_edac.c
index c779092..0804505 100644 (file)
--- a/drivers/edac/i82860_edac.c
+++ b/drivers/edac/i82860_edac.c
@@ -99,6 +99,7 @@ static int i82860_process_error_info(struct mem_ctl_info *mci,
                                struct i82860_error_info *info,
                                int handle_errors)
 {
+       struct dimm_info *dimm;
        int row;
 
        if (!(info->errsts2 & 0x0003))
@@ -108,18 +109,25 @@ static int i82860_process_error_info(struct mem_ctl_info *mci,
                return 1;
 
        if ((info->errsts ^ info->errsts2) & 0x0003) {
-               edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
+               edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
+                                    -1, -1, -1, "UE overwrote CE", "", NULL);
                info->errsts = info->errsts2;
        }
 
        info->eap >>= PAGE_SHIFT;
        row = edac_mc_find_csrow_by_page(mci, info->eap);
+       dimm = mci->csrows[row].channels[0].dimm;
 
        if (info->errsts & 0x0002)
-               edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
+               edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
+                                    info->eap, 0, 0,
+                                    dimm->location[0], dimm->location[1], -1,
+                                    "i82860 UE", "", NULL);
        else
-               edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
-                               "i82860 UE");
+               edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
+                                    info->eap, 0, info->derrsyn,
+                                    dimm->location[0], dimm->location[1], -1,
+                                    "i82860 CE", "", NULL);
 
        return 1;
 }
@@ -140,6 +148,7 @@ static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
        u16 value;
        u32 cumul_size;
        struct csrow_info *csrow;
+       struct dimm_info *dimm;
        int index;
 
        pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
@@ -153,6 +162,8 @@ static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
         */
        for (index = 0; index < mci->nr_csrows; index++) {
                csrow = &mci->csrows[index];
+               dimm = csrow->channels[0].dimm;
+
                pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
                cumul_size = (value & I82860_GBA_MASK) <<
                        (I82860_GBA_SHIFT - PAGE_SHIFT);
@@ -164,30 +175,38 @@ static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
 
                csrow->first_page = last_cumul_size;
                csrow->last_page = cumul_size - 1;
-               csrow->nr_pages = cumul_size - last_cumul_size;
+               dimm->nr_pages = cumul_size - last_cumul_size;
                last_cumul_size = cumul_size;
-               csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
-               csrow->mtype = MEM_RMBS;
-               csrow->dtype = DEV_UNKNOWN;
-               csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
+               dimm->grain = 1 << 12;  /* I82860_EAP has 4KiB reolution */
+               dimm->mtype = MEM_RMBS;
+               dimm->dtype = DEV_UNKNOWN;
+               dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
        }
 }
 
 static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
 {
        struct mem_ctl_info *mci;
+       struct edac_mc_layer layers[2];
        struct i82860_error_info discard;
 
-       /* RDRAM has channels but these don't map onto the abstractions that
-          edac uses.
-          The device groups from the GRA registers seem to map reasonably
-          well onto the notion of a chip select row.
-          There are 16 GRA registers and since the name is associated with
-          the channel and the GRA registers map to physical devices so we are
-          going to make 1 channel for group.
+       /*
+        * RDRAM has channels but these don't map onto the csrow abstraction.
+        * According with the datasheet, there are 2 Rambus channels, supporting
+        * up to 16 direct RDRAM devices.
+        * The device groups from the GRA registers seem to map reasonably
+        * well onto the notion of a chip select row.
+        * There are 16 GRA registers and since the name is associated with
+        * the channel and the GRA registers map to physical devices so we are
+        * going to make 1 channel for group.
         */
-       mci = edac_mc_alloc(0, 16, 1, 0);
-
+       layers[0].type = EDAC_MC_LAYER_CHANNEL;
+       layers[0].size = 2;
+       layers[0].is_virt_csrow = true;
+       layers[1].type = EDAC_MC_LAYER_SLOT;
+       layers[1].size = 8;
+       layers[1].is_virt_csrow = true;
+       mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
        if (!mci)
                return -ENOMEM;