sb_edac: Fix discovery of top-of-low-memory for Haswell

[cascardo/linux.git] / drivers / edac / sb_edac.c

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index e9bb1af..ead0bf9 100644 (file)
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -135,6 +135,7 @@ static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 
 #define TOLM           0x80
 #define        TOHM            0x84
+#define HASWELL_TOLM   0xd0
 #define HASWELL_TOHM_0 0xd4
 #define HASWELL_TOHM_1 0xd8
 
@@ -706,8 +707,8 @@ static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
 {
        u32 reg;
 
-       pci_read_config_dword(pvt->info.pci_vtd, TOLM, &reg);
-       return (GET_BITFIELD(reg, 26, 31) << 26) | 0x1ffffff;
+       pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
+       return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
 }
 
 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
@@ -909,7 +910,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
        u32 reg;
        u64 limit, prv = 0;
        u64 tmp_mb;
-       u32 mb, kb;
+       u32 gb, mb;
        u32 rir_way;
 
        /*
@@ -919,15 +920,17 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
        pvt->tolm = pvt->info.get_tolm(pvt);
        tmp_mb = (1 + pvt->tolm) >> 20;
 
-       mb = div_u64_rem(tmp_mb, 1000, &kb);
-       edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm);
+       gb = div_u64_rem(tmp_mb, 1024, &mb);
+       edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
+               gb, (mb*1000)/1024, (u64)pvt->tolm);
 
        /* Address range is already 45:25 */
        pvt->tohm = pvt->info.get_tohm(pvt);
        tmp_mb = (1 + pvt->tohm) >> 20;
 
-       mb = div_u64_rem(tmp_mb, 1000, &kb);
-       edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm);
+       gb = div_u64_rem(tmp_mb, 1024, &mb);
+       edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
+               gb, (mb*1000)/1024, (u64)pvt->tohm);
 
        /*
         * Step 2) Get SAD range and SAD Interleave list
@@ -949,11 +952,11 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                        break;
 
                tmp_mb = (limit + 1) >> 20;
-               mb = div_u64_rem(tmp_mb, 1000, &kb);
+               gb = div_u64_rem(tmp_mb, 1024, &mb);
                edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
                         n_sads,
                         get_dram_attr(reg),
-                        mb, kb,
+                        gb, (mb*1000)/1024,
                         ((u64)tmp_mb) << 20L,
                         INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
                         reg);
@@ -984,9 +987,9 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                        break;
                tmp_mb = (limit + 1) >> 20;
 
-               mb = div_u64_rem(tmp_mb, 1000, &kb);
+               gb = div_u64_rem(tmp_mb, 1024, &mb);
                edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
-                        n_tads, mb, kb,
+                        n_tads, gb, (mb*1000)/1024,
                         ((u64)tmp_mb) << 20L,
                         (u32)TAD_SOCK(reg),
                         (u32)TAD_CH(reg),
@@ -1009,10 +1012,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                                              tad_ch_nilv_offset[j],
                                              &reg);
                        tmp_mb = TAD_OFFSET(reg) >> 20;
-                       mb = div_u64_rem(tmp_mb, 1000, &kb);
+                       gb = div_u64_rem(tmp_mb, 1024, &mb);
                        edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
                                 i, j,
-                                mb, kb,
+                                gb, (mb*1000)/1024,
                                 ((u64)tmp_mb) << 20L,
                                 reg);
                }
@@ -1034,10 +1037,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
 
                        tmp_mb = pvt->info.rir_limit(reg) >> 20;
                        rir_way = 1 << RIR_WAY(reg);
-                       mb = div_u64_rem(tmp_mb, 1000, &kb);
+                       gb = div_u64_rem(tmp_mb, 1024, &mb);
                        edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
                                 i, j,
-                                mb, kb,
+                                gb, (mb*1000)/1024,
                                 ((u64)tmp_mb) << 20L,
                                 rir_way,
                                 reg);
@@ -1048,10 +1051,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                                                      &reg);
                                tmp_mb = RIR_OFFSET(reg) << 6;
 
-                               mb = div_u64_rem(tmp_mb, 1000, &kb);
+                               gb = div_u64_rem(tmp_mb, 1024, &mb);
                                edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
                                         i, j, k,
-                                        mb, kb,
+                                        gb, (mb*1000)/1024,
                                         ((u64)tmp_mb) << 20L,
                                         (u32)RIR_RNK_TGT(reg),
                                         reg);
@@ -1089,7 +1092,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
        u8                      ch_way, sck_way, pkg, sad_ha = 0;
        u32                     tad_offset;
        u32                     rir_way;
-       u32                     mb, kb;
+       u32                     mb, gb;
        u64                     ch_addr, offset, limit = 0, prv = 0;
 
 
@@ -1358,10 +1361,10 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
                        continue;
 
                limit = pvt->info.rir_limit(reg);
-               mb = div_u64_rem(limit >> 20, 1000, &kb);
+               gb = div_u64_rem(limit >> 20, 1024, &mb);
                edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
                         n_rir,
-                        mb, kb,
+                        gb, (mb*1000)/1024,
                         limit,
                         1 << RIR_WAY(reg));
                if  (ch_addr <= limit)