drm/amdgpu: group BOs by log2 of the size on the LRU v2

[cascardo/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d1ad763..5399f3a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -393,6 +393,14 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
 /*
  * TTM.
  */
+
+#define AMDGPU_TTM_LRU_SIZE    20
+
+struct amdgpu_mman_lru {
+       struct list_head                *lru[TTM_NUM_MEM_TYPES];
+       struct list_head                *swap_lru;
+};
+
 struct amdgpu_mman {
        struct ttm_bo_global_ref        bo_global_ref;
        struct drm_global_reference     mem_global_ref;
@@ -410,6 +418,9 @@ struct amdgpu_mman {
        struct amdgpu_ring                      *buffer_funcs_ring;
        /* Scheduler entity for buffer moves */
        struct amd_sched_entity                 entity;
+
+       /* custom LRU management */
+       struct amdgpu_mman_lru                  log2_size[AMDGPU_TTM_LRU_SIZE];
 };
 
 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
@@ -881,6 +892,7 @@ struct amdgpu_vm_id {
        struct fence            *first;
        struct amdgpu_sync      active;
        struct fence            *last_flush;
+       struct amdgpu_ring      *last_user;
        atomic_long_t           owner;
 
        uint64_t                pd_gpu_addr;
@@ -1037,6 +1049,11 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
  */
 #include "clearstate_defs.h"
 
+struct amdgpu_rlc_funcs {
+       void (*enter_safe_mode)(struct amdgpu_device *adev);
+       void (*exit_safe_mode)(struct amdgpu_device *adev);
+};
+
 struct amdgpu_rlc {
        /* for power gating */
        struct amdgpu_bo        *save_restore_obj;
@@ -1055,6 +1072,10 @@ struct amdgpu_rlc {
        uint64_t                cp_table_gpu_addr;
        volatile uint32_t       *cp_table_ptr;
        u32                     cp_table_size;
+
+       /* safe mode for updating CG/PG state */
+       bool in_safe_mode;
+       const struct amdgpu_rlc_funcs *funcs;
 };
 
 struct amdgpu_mec {
@@ -1593,16 +1614,19 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 /*
  * UVD
  */
-#define AMDGPU_MAX_UVD_HANDLES 10
-#define AMDGPU_UVD_STACK_SIZE  (1024*1024)
-#define AMDGPU_UVD_HEAP_SIZE   (1024*1024)
-#define AMDGPU_UVD_FIRMWARE_OFFSET 256
+#define AMDGPU_DEFAULT_UVD_HANDLES     10
+#define AMDGPU_MAX_UVD_HANDLES         40
+#define AMDGPU_UVD_STACK_SIZE          (200*1024)
+#define AMDGPU_UVD_HEAP_SIZE           (256*1024)
+#define AMDGPU_UVD_SESSION_SIZE                (50*1024)
+#define AMDGPU_UVD_FIRMWARE_OFFSET     256
 
 struct amdgpu_uvd {
        struct amdgpu_bo        *vcpu_bo;
        void                    *cpu_addr;
        uint64_t                gpu_addr;
        void                    *saved_bo;
+       unsigned                max_handles;
        atomic_t                handles[AMDGPU_MAX_UVD_HANDLES];
        struct drm_file         *filp[AMDGPU_MAX_UVD_HANDLES];
        struct delayed_work     idle_work;
@@ -1865,15 +1889,8 @@ struct amdgpu_atcs {
 /*
  * CGS
  */
-void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
-void amdgpu_cgs_destroy_device(void *cgs_device);
-
-
-/*
- * CGS
- */
-void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
-void amdgpu_cgs_destroy_device(void *cgs_device);
+struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
+void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
 
 
 /* GPU virtualization */