Merge branch 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux into drm...

[cascardo/linux.git] / drivers / gpu / drm / amd / amdgpu / dce_v10_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 9d38fe0..613ebb7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -427,16 +427,6 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 
-               if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
-                   connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
-                       /* don't try to enable hpd on eDP or LVDS avoid breaking the
-                        * aux dp channel on imac and help (but not completely fix)
-                        * https://bugzilla.redhat.com/show_bug.cgi?id=726143
-                        * also avoid interrupt storms during dpms.
-                        */
-                       continue;
-               }
-
                switch (amdgpu_connector->hpd.hpd) {
                case AMDGPU_HPD_1:
                        idx = 0;
@@ -460,6 +450,19 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
                        continue;
                }
 
+               if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
+                   connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
+                       /* don't try to enable hpd on eDP or LVDS avoid breaking the
+                        * aux dp channel on imac and help (but not completely fix)
+                        * https://bugzilla.redhat.com/show_bug.cgi?id=726143
+                        * also avoid interrupt storms during dpms.
+                        */
+                       tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
+                       tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
+                       WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
+                       continue;
+               }
+
                tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
                tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
                WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
@@ -2104,7 +2107,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
        struct amdgpu_framebuffer *amdgpu_fb;
        struct drm_framebuffer *target_fb;
        struct drm_gem_object *obj;
-       struct amdgpu_bo *rbo;
+       struct amdgpu_bo *abo;
        uint64_t fb_location, tiling_flags;
        uint32_t fb_format, fb_pitch_pixels;
        u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
@@ -2132,23 +2135,23 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
         * just update base pointers
         */
        obj = amdgpu_fb->obj;
-       rbo = gem_to_amdgpu_bo(obj);
-       r = amdgpu_bo_reserve(rbo, false);
+       abo = gem_to_amdgpu_bo(obj);
+       r = amdgpu_bo_reserve(abo, false);
        if (unlikely(r != 0))
                return r;
 
        if (atomic) {
-               fb_location = amdgpu_bo_gpu_offset(rbo);
+               fb_location = amdgpu_bo_gpu_offset(abo);
        } else {
-               r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
+               r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
                if (unlikely(r != 0)) {
-                       amdgpu_bo_unreserve(rbo);
+                       amdgpu_bo_unreserve(abo);
                        return -EINVAL;
                }
        }
 
-       amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
-       amdgpu_bo_unreserve(rbo);
+       amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
+       amdgpu_bo_unreserve(abo);
 
        pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
 
@@ -2323,12 +2326,12 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
 
        if (!atomic && fb && fb != crtc->primary->fb) {
                amdgpu_fb = to_amdgpu_framebuffer(fb);
-               rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
-               r = amdgpu_bo_reserve(rbo, false);
+               abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
+               r = amdgpu_bo_reserve(abo, false);
                if (unlikely(r != 0))
                        return r;
-               amdgpu_bo_unpin(rbo);
-               amdgpu_bo_unreserve(rbo);
+               amdgpu_bo_unpin(abo);
+               amdgpu_bo_unreserve(abo);
        }
 
        /* Bytes per pixel may have changed */
@@ -2808,16 +2811,16 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
        if (crtc->primary->fb) {
                int r;
                struct amdgpu_framebuffer *amdgpu_fb;
-               struct amdgpu_bo *rbo;
+               struct amdgpu_bo *abo;
 
                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
-               rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
-               r = amdgpu_bo_reserve(rbo, false);
+               abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
+               r = amdgpu_bo_reserve(abo, false);
                if (unlikely(r))
-                       DRM_ERROR("failed to reserve rbo before unpin\n");
+                       DRM_ERROR("failed to reserve abo before unpin\n");
                else {
-                       amdgpu_bo_unpin(rbo);
-                       amdgpu_bo_unreserve(rbo);
+                       amdgpu_bo_unpin(abo);
+                       amdgpu_bo_unreserve(abo);
                }
        }
        /* disable the GRPH */