drm/i915: Convert dev_priv->dev backpointers to dev_priv->drm

[cascardo/linux.git] / drivers / gpu / drm / i915 / i915_gem_render_state.c

diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 71611bf..f75bbd6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -29,7 +29,7 @@
 #include "intel_renderstate.h"
 
 static const struct intel_renderstate_rodata *
-render_state_get_rodata(struct drm_device *dev, const int gen)
+render_state_get_rodata(const int gen)
 {
        switch (gen) {
        case 6:
@@ -45,21 +45,22 @@ render_state_get_rodata(struct drm_device *dev, const int gen)
        return NULL;
 }
 
-static int render_state_init(struct render_state *so, struct drm_device *dev)
+static int render_state_init(struct render_state *so,
+                            struct drm_i915_private *dev_priv)
 {
        int ret;
 
-       so->gen = INTEL_INFO(dev)->gen;
-       so->rodata = render_state_get_rodata(dev, so->gen);
+       so->gen = INTEL_GEN(dev_priv);
+       so->rodata = render_state_get_rodata(so->gen);
        if (so->rodata == NULL)
                return 0;
 
        if (so->rodata->batch_items * 4 > 4096)
                return -EINVAL;
 
-       so->obj = i915_gem_alloc_object(dev, 4096);
-       if (so->obj == NULL)
-               return -ENOMEM;
+       so->obj = i915_gem_object_create(&dev_priv->drm, 4096);
+       if (IS_ERR(so->obj))
+               return PTR_ERR(so->obj);
 
        ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0);
        if (ret)
@@ -93,6 +94,7 @@ free_gem:
 
 static int render_state_setup(struct render_state *so)
 {
+       struct drm_device *dev = so->obj->base.dev;
        const struct intel_renderstate_rodata *rodata = so->rodata;
        unsigned int i = 0, reloc_index = 0;
        struct page *page;
@@ -134,6 +136,33 @@ static int render_state_setup(struct render_state *so)
 
        so->aux_batch_offset = i * sizeof(u32);
 
+       if (HAS_POOLED_EU(dev)) {
+               /*
+                * We always program 3x6 pool config but depending upon which
+                * subslice is disabled HW drops down to appropriate config
+                * shown below.
+                *
+                * In the below table 2x6 config always refers to
+                * fused-down version, native 2x6 is not available and can
+                * be ignored
+                *
+                * SNo  subslices config                eu pool configuration
+                * -----------------------------------------------------------
+                * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
+                * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
+                * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
+                * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
+                */
+               u32 eu_pool_config = 0x00777000;
+
+               OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
+               OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
+               OUT_BATCH(d, i, eu_pool_config);
+               OUT_BATCH(d, i, 0);
+               OUT_BATCH(d, i, 0);
+               OUT_BATCH(d, i, 0);
+       }
+
        OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
        so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
 
@@ -177,7 +206,7 @@ int i915_gem_render_state_prepare(struct intel_engine_cs *engine,
        if (WARN_ON(engine->id != RCS))
                return -ENOENT;
 
-       ret = render_state_init(so, engine->dev);
+       ret = render_state_init(so, engine->i915);
        if (ret)
                return ret;