drm/i915: Convert dev_priv->dev backpointers to dev_priv->drm

[cascardo/linux.git] / drivers / gpu / drm / i915 / i915_gem_render_state.c

diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 7c93327..f75bbd6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -58,7 +58,7 @@ static int render_state_init(struct render_state *so,
        if (so->rodata->batch_items * 4 > 4096)
                return -EINVAL;
 
-       so->obj = i915_gem_object_create(dev_priv->dev, 4096);
+       so->obj = i915_gem_object_create(&dev_priv->drm, 4096);
        if (IS_ERR(so->obj))
                return PTR_ERR(so->obj);
 
@@ -94,6 +94,7 @@ free_gem:
 
 static int render_state_setup(struct render_state *so)
 {
+       struct drm_device *dev = so->obj->base.dev;
        const struct intel_renderstate_rodata *rodata = so->rodata;
        unsigned int i = 0, reloc_index = 0;
        struct page *page;
@@ -135,6 +136,33 @@ static int render_state_setup(struct render_state *so)
 
        so->aux_batch_offset = i * sizeof(u32);
 
+       if (HAS_POOLED_EU(dev)) {
+               /*
+                * We always program 3x6 pool config but depending upon which
+                * subslice is disabled HW drops down to appropriate config
+                * shown below.
+                *
+                * In the below table 2x6 config always refers to
+                * fused-down version, native 2x6 is not available and can
+                * be ignored
+                *
+                * SNo  subslices config                eu pool configuration
+                * -----------------------------------------------------------
+                * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
+                * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
+                * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
+                * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
+                */
+               u32 eu_pool_config = 0x00777000;
+
+               OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
+               OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
+               OUT_BATCH(d, i, eu_pool_config);
+               OUT_BATCH(d, i, 0);
+               OUT_BATCH(d, i, 0);
+               OUT_BATCH(d, i, 0);
+       }
+
        OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
        so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;