drm/i915: implement ibx_hpd_irq_setup

[cascardo/linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176cf5c..9703307 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -121,6 +121,7 @@
 
 #define GAM_ECOCHK                     0x4090
 #define   ECOCHK_SNB_BIT               (1<<10)
+#define   HSW_ECOCHK_ARB_PRIO_SOL      (1<<6)
 #define   ECOCHK_PPGTT_CACHE64B                (0x3<<3)
 #define   ECOCHK_PPGTT_CACHE4B         (0x0<<3)
 
@@ -1641,6 +1642,12 @@
 #define   SDVOC_HOTPLUG_INT_EN                 (1 << 25)
 #define   TV_HOTPLUG_INT_EN                    (1 << 18)
 #define   CRT_HOTPLUG_INT_EN                   (1 << 9)
+#define HOTPLUG_INT_EN_MASK                    (PORTB_HOTPLUG_INT_EN | \
+                                                PORTC_HOTPLUG_INT_EN | \
+                                                PORTD_HOTPLUG_INT_EN | \
+                                                SDVOC_HOTPLUG_INT_EN | \
+                                                SDVOB_HOTPLUG_INT_EN | \
+                                                CRT_HOTPLUG_INT_EN)
 #define   CRT_HOTPLUG_FORCE_DETECT             (1 << 3)
 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32       (0 << 8)
 /* must use period 64 on GM45 according to docs */
@@ -1679,6 +1686,26 @@
 #define   SDVOB_HOTPLUG_INT_STATUS_I965                (3 << 2)
 #define   SDVOC_HOTPLUG_INT_STATUS_I915                (1 << 7)
 #define   SDVOB_HOTPLUG_INT_STATUS_I915                (1 << 6)
+#define   HOTPLUG_INT_STATUS_G4X               (CRT_HOTPLUG_INT_STATUS | \
+                                                SDVOB_HOTPLUG_INT_STATUS_G4X | \
+                                                SDVOC_HOTPLUG_INT_STATUS_G4X | \
+                                                PORTB_HOTPLUG_INT_STATUS | \
+                                                PORTC_HOTPLUG_INT_STATUS | \
+                                                PORTD_HOTPLUG_INT_STATUS)
+
+#define HOTPLUG_INT_STATUS_I965                        (CRT_HOTPLUG_INT_STATUS | \
+                                                SDVOB_HOTPLUG_INT_STATUS_I965 | \
+                                                SDVOC_HOTPLUG_INT_STATUS_I965 | \
+                                                PORTB_HOTPLUG_INT_STATUS | \
+                                                PORTC_HOTPLUG_INT_STATUS | \
+                                                PORTD_HOTPLUG_INT_STATUS)
+
+#define HOTPLUG_INT_STATUS_I915                        (CRT_HOTPLUG_INT_STATUS | \
+                                                SDVOB_HOTPLUG_INT_STATUS_I915 | \
+                                                SDVOC_HOTPLUG_INT_STATUS_I915 | \
+                                                PORTB_HOTPLUG_INT_STATUS | \
+                                                PORTC_HOTPLUG_INT_STATUS | \
+                                                PORTD_HOTPLUG_INT_STATUS)
 
 /* SDVO and HDMI port control.
  * The same register may be used for SDVO or HDMI */
@@ -1923,7 +1950,7 @@
 #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
 
 /* Backlight control */
-#define BLC_PWM_CTL2           0x61250 /* 965+ only */
+#define BLC_PWM_CTL2   (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
 #define   BLM_PWM_ENABLE               (1 << 31)
 #define   BLM_COMBINATION_MODE         (1 << 30) /* gen4 only */
 #define   BLM_PIPE_SELECT              (1 << 29)
@@ -1942,7 +1969,7 @@
 #define   BLM_PHASE_IN_COUNT_MASK      (0xff << 8)
 #define   BLM_PHASE_IN_INCR_SHIFT      (0)
 #define   BLM_PHASE_IN_INCR_MASK       (0xff << 0)
-#define BLC_PWM_CTL            0x61254
+#define BLC_PWM_CTL    (dev_priv->info->display_mmio_offset + 0x61254)
 /*
  * This is the most significant 15 bits of the number of backlight cycles in a
  * complete cycle of the modulated backlight control.
@@ -1964,7 +1991,7 @@
 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV                (0xfffe)
 #define   BLM_POLARITY_PNV                     (1 << 0) /* pnv only */
 
-#define BLC_HIST_CTL           0x61260
+#define BLC_HIST_CTL   (dev_priv->info->display_mmio_offset + 0x61260)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the
  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
@@ -2801,6 +2828,8 @@
 #define   DSPFW_HPLL_CURSOR_SHIFT      16
 #define   DSPFW_HPLL_CURSOR_MASK       (0x3f<<16)
 #define   DSPFW_HPLL_SR_MASK           (0x1ff)
+#define DSPFW4                 (dev_priv->info->display_mmio_offset + 0x70070)
+#define DSPFW7                 (dev_priv->info->display_mmio_offset + 0x7007c)
 
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32     32
@@ -3533,7 +3562,11 @@
 #define SDE_PORTC_HOTPLUG       (1 << 9)
 #define SDE_PORTB_HOTPLUG       (1 << 8)
 #define SDE_SDVOB_HOTPLUG       (1 << 6)
-#define SDE_HOTPLUG_MASK       (0xf << 8)
+#define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
+                                SDE_SDVOB_HOTPLUG |    \
+                                SDE_PORTB_HOTPLUG |    \
+                                SDE_PORTC_HOTPLUG |    \
+                                SDE_PORTD_HOTPLUG)
 #define SDE_TRANSB_CRC_DONE    (1 << 5)
 #define SDE_TRANSB_CRC_ERR     (1 << 4)
 #define SDE_TRANSB_FIFO_UNDER  (1 << 3)
@@ -4148,6 +4181,8 @@
 #define  FORCEWAKE                             0xA18C
 #define  FORCEWAKE_VLV                         0x1300b0
 #define  FORCEWAKE_ACK_VLV                     0x1300b4
+#define  FORCEWAKE_MEDIA_VLV                   0x1300b8
+#define  FORCEWAKE_ACK_MEDIA_VLV               0x1300bc
 #define  FORCEWAKE_ACK_HSW                     0x130044
 #define  FORCEWAKE_ACK                         0x130090
 #define  VLV_GTLC_WAKE_CTRL                    0x130090
@@ -4185,6 +4220,7 @@
 #define GEN6_RPNSWREQ                          0xA008
 #define   GEN6_TURBO_DISABLE                   (1<<31)
 #define   GEN6_FREQUENCY(x)                    ((x)<<25)
+#define   HSW_FREQUENCY(x)                     ((x)<<24)
 #define   GEN6_OFFSET(x)                       ((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO                        (0<<15)
 #define GEN6_RC_VIDEO_FREQ                     0xA00C