Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next

[cascardo/linux.git] / drivers / gpu / drm / i915 / intel_bios.c

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b3e437b..68421c2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -42,7 +42,7 @@ find_section(const void *_bdb, int section_id)
        const struct bdb_header *bdb = _bdb;
        const u8 *base = _bdb;
        int index = 0;
-       u16 total, current_size;
+       u32 total, current_size;
        u8 current_id;
 
        /* skip to first section */
@@ -57,6 +57,10 @@ find_section(const void *_bdb, int section_id)
                current_size = *((const u16 *)(base + index));
                index += 2;
 
+               /* The MIPI Sequence Block v3+ has a separate size field. */
+               if (current_id == BDB_MIPI_SEQUENCE && *(base + index) >= 3)
+                       current_size = *((const u32 *)(base + index + 1));
+
                if (index + current_size > total)
                        return NULL;
 
@@ -799,6 +803,12 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
                return;
        }
 
+       /* Fail gracefully for forward incompatible sequence block. */
+       if (sequence->version >= 3) {
+               DRM_ERROR("Unable to parse MIPI Sequence Block v3+\n");
+               return;
+       }
+
        DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
 
        block_size = get_blocksize(sequence);
@@ -1340,21 +1350,3 @@ intel_parse_bios(struct drm_device *dev)
 
        return 0;
 }
-
-/* Ensure that vital registers have been initialised, even if the BIOS
- * is absent or just failing to do its job.
- */
-void intel_setup_bios(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-        /* Set the Panel Power On/Off timings if uninitialized. */
-       if (!HAS_PCH_SPLIT(dev) &&
-           I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
-               /* Set T2 to 40ms and T5 to 200ms */
-               I915_WRITE(PP_ON_DELAYS, 0x019007d0);
-
-               /* Set T3 to 35ms and Tx to 200ms */
-               I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
-       }
-}