Merge branch 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux into drm...

[cascardo/linux.git] / drivers / gpu / drm / i915 / intel_mocs.c

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 927825f..80bb924 100644 (file)
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -97,7 +97,8 @@ struct drm_i915_mocs_table {
  *       end.
  */
 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-       { /* 0x00000009 */
+       [I915_MOCS_UNCACHED] = {
+         /* 0x00000009 */
          .control_value = LE_CACHEABILITY(LE_UC) |
                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
                           LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
@@ -106,7 +107,7 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
          /* 0x0010 */
          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
        },
-       {
+       [I915_MOCS_PTE] = {
          /* 0x00000038 */
          .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
@@ -115,7 +116,7 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
          /* 0x0030 */
          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
        },
-       {
+       [I915_MOCS_CACHED] = {
          /* 0x0000003b */
          .control_value = LE_CACHEABILITY(LE_WB) |
                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
@@ -128,7 +129,7 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
 
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-       {
+       [I915_MOCS_UNCACHED] = {
          /* 0x00000009 */
          .control_value = LE_CACHEABILITY(LE_UC) |
                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
@@ -138,7 +139,7 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
          /* 0x0010 */
          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
        },
-       {
+       [I915_MOCS_PTE] = {
          /* 0x00000038 */
          .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
@@ -148,7 +149,7 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
          /* 0x0030 */
          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
        },
-       {
+       [I915_MOCS_CACHED] = {
          /* 0x00000039 */
          .control_value = LE_CACHEABILITY(LE_UC) |
                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
@@ -203,9 +204,9 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
        return result;
 }
 
-static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
+static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
 {
-       switch (ring) {
+       switch (engine_id) {
        case RCS:
                return GEN9_GFX_MOCS(index);
        case VCS:
@@ -217,7 +218,7 @@ static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
        case VCS2:
                return GEN9_MFX1_MOCS(index);
        default:
-               MISSING_CASE(ring);
+               MISSING_CASE(engine_id);
                return INVALID_MMIO_REG;
        }
 }
@@ -275,7 +276,7 @@ int intel_mocs_init_engine(struct intel_engine_cs *engine)
 static int emit_mocs_control_table(struct drm_i915_gem_request *req,
                                   const struct drm_i915_mocs_table *table)
 {
-       struct intel_ringbuffer *ringbuf = req->ringbuf;
+       struct intel_ring *ring = req->ring;
        enum intel_engine_id engine = req->engine->id;
        unsigned int index;
        int ret;
@@ -287,14 +288,11 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
        if (ret)
                return ret;
 
-       intel_logical_ring_emit(ringbuf,
-                               MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
+       intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
 
        for (index = 0; index < table->size; index++) {
-               intel_logical_ring_emit_reg(ringbuf,
-                                           mocs_register(engine, index));
-               intel_logical_ring_emit(ringbuf,
-                                       table->table[index].control_value);
+               intel_ring_emit_reg(ring, mocs_register(engine, index));
+               intel_ring_emit(ring, table->table[index].control_value);
        }
 
        /*
@@ -306,14 +304,12 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
         * that value to all the used entries.
         */
        for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
-               intel_logical_ring_emit_reg(ringbuf,
-                                           mocs_register(engine, index));
-               intel_logical_ring_emit(ringbuf,
-                                       table->table[0].control_value);
+               intel_ring_emit_reg(ring, mocs_register(engine, index));
+               intel_ring_emit(ring, table->table[0].control_value);
        }
 
-       intel_logical_ring_emit(ringbuf, MI_NOOP);
-       intel_logical_ring_advance(ringbuf);
+       intel_ring_emit(ring, MI_NOOP);
+       intel_ring_advance(ring);
 
        return 0;
 }
@@ -340,7 +336,7 @@ static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
 static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
                                const struct drm_i915_mocs_table *table)
 {
-       struct intel_ringbuffer *ringbuf = req->ringbuf;
+       struct intel_ring *ring = req->ring;
        unsigned int i;
        int ret;
 
@@ -351,19 +347,18 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
        if (ret)
                return ret;
 
-       intel_logical_ring_emit(ringbuf,
+       intel_ring_emit(ring,
                        MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
 
        for (i = 0; i < table->size/2; i++) {
-               intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
-               intel_logical_ring_emit(ringbuf,
-                                       l3cc_combine(table, 2*i, 2*i+1));
+               intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
+               intel_ring_emit(ring, l3cc_combine(table, 2*i, 2*i+1));
        }
 
        if (table->size & 0x01) {
                /* Odd table size - 1 left over */
-               intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
-               intel_logical_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0));
+               intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
+               intel_ring_emit(ring, l3cc_combine(table, 2*i, 0));
                i++;
        }
 
@@ -373,12 +368,12 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
         * they are reserved by the hardware.
         */
        for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
-               intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
-               intel_logical_ring_emit(ringbuf, l3cc_combine(table, 0, 0));
+               intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
+               intel_ring_emit(ring, l3cc_combine(table, 0, 0));
        }
 
-       intel_logical_ring_emit(ringbuf, MI_NOOP);
-       intel_logical_ring_advance(ringbuf);
+       intel_ring_emit(ring, MI_NOOP);
+       intel_ring_advance(ring);
 
        return 0;
 }