drm/nv50-/disp: move DP link training to core and train from supervisor
[cascardo/linux.git] / drivers / gpu / drm / nouveau / core / engine / disp / nve0.c
index 259537c..20725b3 100644 (file)
@@ -51,10 +51,11 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
               struct nouveau_object **pobject)
 {
        struct nv50_disp_priv *priv;
+       int heads = nv_rd32(parent, 0x022448);
        int ret;
 
-       ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
-                                 "display", &priv);
+       ret = nouveau_disp_create(parent, engine, oclass, heads,
+                                 "PDISP", "display", &priv);
        *pobject = nv_object(priv);
        if (ret)
                return ret;
@@ -62,8 +63,9 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        nv_engine(priv)->sclass = nve0_disp_base_oclass;
        nv_engine(priv)->cclass = &nv50_disp_cclass;
        nv_subdev(priv)->intr = nvd0_disp_intr;
+       INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
        priv->sclass = nve0_disp_sclass;
-       priv->head.nr = nv_rd32(priv, 0x022448);
+       priv->head.nr = heads;
        priv->dac.nr = 3;
        priv->sor.nr = 4;
        priv->dac.power = nv50_dac_power;
@@ -71,14 +73,7 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->sor.power = nv50_sor_power;
        priv->sor.hda_eld = nvd0_hda_eld;
        priv->sor.hdmi = nvd0_hdmi_ctrl;
-       priv->sor.dp_train = nvd0_sor_dp_train;
-       priv->sor.dp_train_init = nv94_sor_dp_train_init;
-       priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
-       priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;
-       priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;
-
-       INIT_LIST_HEAD(&priv->base.vblank.list);
-       spin_lock_init(&priv->base.vblank.lock);
+       priv->sor.dp = &nvd0_sor_dp_func;
        return 0;
 }