t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
/* XXX: P.version == 1 only has DDR2 and GDDR3? */
- if (pfb->ram.type == NV_MEM_TYPE_DDR2) {
+ if (pfb->ram->type == NV_MEM_TYPE_DDR2) {
t->reg[5] |= (e->tCL + 3) << 8;
t->reg[6] |= (t->tCWL - 2) << 8;
t->reg[8] |= (e->tCL - 4);
break;
}
- switch (pfb->ram.type * !ret) {
+ switch (pfb->ram->type * !ret) {
case NV_MEM_TYPE_GDDR3:
ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
break;
else
dll_off = !!(ramcfg[2] & 0x40);
- switch (pfb->ram.type) {
+ switch (pfb->ram->type) {
case NV_MEM_TYPE_GDDR3:
t->mr[1] &= ~0x00000040;
t->mr[1] |= 0x00000040 * dll_off;
t->odt = 0;
t->drive_strength = 0;
- switch (pfb->ram.type) {
+ switch (pfb->ram->type) {
case NV_MEM_TYPE_DDR3:
t->odt |= (t->mr[1] & 0x200) >> 7;
case NV_MEM_TYPE_DDR2:
u32 mr[3] = { info->mr[0], info->mr[1], info->mr[2] };
u32 mr1_dlloff;
- switch (pfb->ram.type) {
+ switch (pfb->ram->type) {
case NV_MEM_TYPE_DDR2:
tDLLK = 2000;
mr1_dlloff = 0x00000001;
}
/* fetch current MRs */
- switch (pfb->ram.type) {
+ switch (pfb->ram->type) {
case NV_MEM_TYPE_GDDR3:
case NV_MEM_TYPE_DDR3:
mr[2] = exec->mrg(exec, 2);
exec->mrs (exec, 0, info->mr[0] | 0x00000000);
exec->wait(exec, tMRD);
exec->wait(exec, tDLLK);
- if (pfb->ram.type == NV_MEM_TYPE_GDDR3)
+ if (pfb->ram->type == NV_MEM_TYPE_GDDR3)
exec->precharge(exec);
}