*
* Author Matt Henderson & Guy Ellis
* Copyright by Traverse Technologies Pty Ltd, www.travers.com.au
- *
+ *
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
icc_new_ph(struct IsdnCardState *cs)
{
switch (cs->dc.icc.ph_state) {
- case (ICC_IND_EI1):
- ph_command(cs, ICC_CMD_DI);
- l1_msg(cs, HW_RESET | INDICATION, NULL);
- break;
- case (ICC_IND_DC):
- l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
- break;
- case (ICC_IND_DR):
- l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
- break;
- case (ICC_IND_PU):
- l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
- break;
- case (ICC_IND_FJ):
- l1_msg(cs, HW_RSYNC | INDICATION, NULL);
- break;
- case (ICC_IND_AR):
- l1_msg(cs, HW_INFO2 | INDICATION, NULL);
- break;
- case (ICC_IND_AI):
- l1_msg(cs, HW_INFO4 | INDICATION, NULL);
- break;
- default:
- break;
+ case (ICC_IND_EI1):
+ ph_command(cs, ICC_CMD_DI);
+ l1_msg(cs, HW_RESET | INDICATION, NULL);
+ break;
+ case (ICC_IND_DC):
+ l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
+ break;
+ case (ICC_IND_DR):
+ l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
+ break;
+ case (ICC_IND_PU):
+ l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
+ break;
+ case (ICC_IND_FJ):
+ l1_msg(cs, HW_RSYNC | INDICATION, NULL);
+ break;
+ case (ICC_IND_AR):
+ l1_msg(cs, HW_INFO2 | INDICATION, NULL);
+ break;
+ case (ICC_IND_AI):
+ l1_msg(cs, HW_INFO4 | INDICATION, NULL);
+ break;
+ default:
+ break;
}
}
struct IsdnCardState *cs =
container_of(work, struct IsdnCardState, tqueue);
struct PStack *stptr;
-
+
if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
if (cs->debug)
debugl1(cs, "D-Channel Busy cleared");
}
}
if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
- icc_new_ph(cs);
+ icc_new_ph(cs);
if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
DChannel_proc_rcv(cs);
if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
} else
schedule_event(cs, D_XMTBUFREADY);
}
- afterXPR:
+afterXPR:
if (val & 0x04) { /* CISQ */
exval = cs->readisac(cs, ICC_CIR0);
if (cs->debug & L1_DEB_ISAC)
- debugl1(cs, "ICC CIR0 %02X", exval );
+ debugl1(cs, "ICC CIR0 %02X", exval);
if (exval & 2) {
cs->dc.icc.ph_state = (exval >> 2) & 0xf;
if (cs->debug & L1_DEB_ISAC)
if (exval & 1) {
exval = cs->readisac(cs, ICC_CIR1);
if (cs->debug & L1_DEB_ISAC)
- debugl1(cs, "ICC CIR1 %02X", exval );
+ debugl1(cs, "ICC CIR1 %02X", exval);
}
}
if (val & 0x02) { /* SIN */
}
cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0);
if (cs->debug & L1_DEB_MONITOR)
- debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);
+ debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]);
if (cs->dc.icc.mon_rxp == 1) {
cs->dc.icc.mocr |= 0x04;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
}
}
- afterMONR0:
+ afterMONR0:
if (v1 & 0x80) {
if (!cs->dc.icc.mon_rx) {
if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
}
cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1);
if (cs->debug & L1_DEB_MONITOR)
- debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);
+ debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]);
cs->dc.icc.mocr |= 0x40;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
}
- afterMONR1:
+ afterMONR1:
if (v1 & 0x04) {
cs->dc.icc.mocr &= 0xf0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
schedule_event(cs, D_RX_MON1);
}
if (v1 & 0x02) {
- if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
- (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
- !(v1 & 0x08))) {
+ if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
+ (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
+ !(v1 & 0x08))) {
cs->dc.icc.mocr &= 0xf0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mocr |= 0x0a;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
if (cs->dc.icc.mon_txc &&
- (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
+ (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
schedule_event(cs, D_TX_MON0);
goto AfterMOX0;
}
goto AfterMOX0;
}
cs->writeisac(cs, ICC_MOX0,
- cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
+ cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
if (cs->debug & L1_DEB_MONITOR)
- debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);
+ debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]);
}
- AfterMOX0:
+ AfterMOX0:
if (v1 & 0x20) {
- if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
- (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
- !(v1 & 0x80))) {
+ if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
+ (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
+ !(v1 & 0x80))) {
cs->dc.icc.mocr &= 0x0f;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mocr |= 0xa0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
if (cs->dc.icc.mon_txc &&
- (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
+ (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
schedule_event(cs, D_TX_MON1);
goto AfterMOX1;
}
goto AfterMOX1;
}
cs->writeisac(cs, ICC_MOX1,
- cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
+ cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
if (cs->debug & L1_DEB_MONITOR)
- debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);
+ debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]);
}
- AfterMOX1:
+ AfterMOX1:
#endif
}
}
int val;
switch (pr) {
- case (PH_DATA |REQUEST):
- if (cs->debug & DEB_DLOG_HEX)
- LogFrame(cs, skb->data, skb->len);
- if (cs->debug & DEB_DLOG_VERBOSE)
- dlogframe(cs, skb, 0);
- spin_lock_irqsave(&cs->lock, flags);
- if (cs->tx_skb) {
- skb_queue_tail(&cs->sq, skb);
-#ifdef L2FRAME_DEBUG /* psa */
- if (cs->debug & L1_DEB_LAPD)
- Logl2Frame(cs, skb, "PH_DATA Queued", 0);
-#endif
- } else {
- cs->tx_skb = skb;
- cs->tx_cnt = 0;
+ case (PH_DATA | REQUEST):
+ if (cs->debug & DEB_DLOG_HEX)
+ LogFrame(cs, skb->data, skb->len);
+ if (cs->debug & DEB_DLOG_VERBOSE)
+ dlogframe(cs, skb, 0);
+ spin_lock_irqsave(&cs->lock, flags);
+ if (cs->tx_skb) {
+ skb_queue_tail(&cs->sq, skb);
#ifdef L2FRAME_DEBUG /* psa */
- if (cs->debug & L1_DEB_LAPD)
- Logl2Frame(cs, skb, "PH_DATA", 0);
+ if (cs->debug & L1_DEB_LAPD)
+ Logl2Frame(cs, skb, "PH_DATA Queued", 0);
#endif
- icc_fill_fifo(cs);
- }
- spin_unlock_irqrestore(&cs->lock, flags);
- break;
- case (PH_PULL |INDICATION):
- spin_lock_irqsave(&cs->lock, flags);
- if (cs->tx_skb) {
- if (cs->debug & L1_DEB_WARN)
- debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
- skb_queue_tail(&cs->sq, skb);
- spin_unlock_irqrestore(&cs->lock, flags);
- break;
- }
- if (cs->debug & DEB_DLOG_HEX)
- LogFrame(cs, skb->data, skb->len);
- if (cs->debug & DEB_DLOG_VERBOSE)
- dlogframe(cs, skb, 0);
+ } else {
cs->tx_skb = skb;
cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG /* psa */
if (cs->debug & L1_DEB_LAPD)
- Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
+ Logl2Frame(cs, skb, "PH_DATA", 0);
#endif
icc_fill_fifo(cs);
+ }
+ spin_unlock_irqrestore(&cs->lock, flags);
+ break;
+ case (PH_PULL | INDICATION):
+ spin_lock_irqsave(&cs->lock, flags);
+ if (cs->tx_skb) {
+ if (cs->debug & L1_DEB_WARN)
+ debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
+ skb_queue_tail(&cs->sq, skb);
spin_unlock_irqrestore(&cs->lock, flags);
break;
- case (PH_PULL | REQUEST):
+ }
+ if (cs->debug & DEB_DLOG_HEX)
+ LogFrame(cs, skb->data, skb->len);
+ if (cs->debug & DEB_DLOG_VERBOSE)
+ dlogframe(cs, skb, 0);
+ cs->tx_skb = skb;
+ cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG /* psa */
- if (cs->debug & L1_DEB_LAPD)
- debugl1(cs, "-> PH_REQUEST_PULL");
+ if (cs->debug & L1_DEB_LAPD)
+ Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
#endif
- if (!cs->tx_skb) {
- test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
- st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
- } else
- test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
- break;
- case (HW_RESET | REQUEST):
- spin_lock_irqsave(&cs->lock, flags);
- if ((cs->dc.icc.ph_state == ICC_IND_EI1) ||
- (cs->dc.icc.ph_state == ICC_IND_DR))
- ph_command(cs, ICC_CMD_DI);
- else
- ph_command(cs, ICC_CMD_RES);
- spin_unlock_irqrestore(&cs->lock, flags);
- break;
- case (HW_ENABLE | REQUEST):
- spin_lock_irqsave(&cs->lock, flags);
+ icc_fill_fifo(cs);
+ spin_unlock_irqrestore(&cs->lock, flags);
+ break;
+ case (PH_PULL | REQUEST):
+#ifdef L2FRAME_DEBUG /* psa */
+ if (cs->debug & L1_DEB_LAPD)
+ debugl1(cs, "-> PH_REQUEST_PULL");
+#endif
+ if (!cs->tx_skb) {
+ test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
+ st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
+ } else
+ test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
+ break;
+ case (HW_RESET | REQUEST):
+ spin_lock_irqsave(&cs->lock, flags);
+ if ((cs->dc.icc.ph_state == ICC_IND_EI1) ||
+ (cs->dc.icc.ph_state == ICC_IND_DR))
ph_command(cs, ICC_CMD_DI);
- spin_unlock_irqrestore(&cs->lock, flags);
- break;
- case (HW_INFO1 | REQUEST):
- spin_lock_irqsave(&cs->lock, flags);
- ph_command(cs, ICC_CMD_AR);
- spin_unlock_irqrestore(&cs->lock, flags);
- break;
- case (HW_INFO3 | REQUEST):
- spin_lock_irqsave(&cs->lock, flags);
- ph_command(cs, ICC_CMD_AI);
- spin_unlock_irqrestore(&cs->lock, flags);
- break;
- case (HW_TESTLOOP | REQUEST):
- spin_lock_irqsave(&cs->lock, flags);
- val = 0;
- if (1 & (long) arg)
- val |= 0x0c;
- if (2 & (long) arg)
- val |= 0x3;
- if (test_bit(HW_IOM1, &cs->HW_Flags)) {
- /* IOM 1 Mode */
- if (!val) {
- cs->writeisac(cs, ICC_SPCR, 0xa);
- cs->writeisac(cs, ICC_ADF1, 0x2);
- } else {
- cs->writeisac(cs, ICC_SPCR, val);
- cs->writeisac(cs, ICC_ADF1, 0xa);
- }
+ else
+ ph_command(cs, ICC_CMD_RES);
+ spin_unlock_irqrestore(&cs->lock, flags);
+ break;
+ case (HW_ENABLE | REQUEST):
+ spin_lock_irqsave(&cs->lock, flags);
+ ph_command(cs, ICC_CMD_DI);
+ spin_unlock_irqrestore(&cs->lock, flags);
+ break;
+ case (HW_INFO1 | REQUEST):
+ spin_lock_irqsave(&cs->lock, flags);
+ ph_command(cs, ICC_CMD_AR);
+ spin_unlock_irqrestore(&cs->lock, flags);
+ break;
+ case (HW_INFO3 | REQUEST):
+ spin_lock_irqsave(&cs->lock, flags);
+ ph_command(cs, ICC_CMD_AI);
+ spin_unlock_irqrestore(&cs->lock, flags);
+ break;
+ case (HW_TESTLOOP | REQUEST):
+ spin_lock_irqsave(&cs->lock, flags);
+ val = 0;
+ if (1 & (long) arg)
+ val |= 0x0c;
+ if (2 & (long) arg)
+ val |= 0x3;
+ if (test_bit(HW_IOM1, &cs->HW_Flags)) {
+ /* IOM 1 Mode */
+ if (!val) {
+ cs->writeisac(cs, ICC_SPCR, 0xa);
+ cs->writeisac(cs, ICC_ADF1, 0x2);
} else {
- /* IOM 2 Mode */
cs->writeisac(cs, ICC_SPCR, val);
- if (val)
- cs->writeisac(cs, ICC_ADF1, 0x8);
- else
- cs->writeisac(cs, ICC_ADF1, 0x0);
- }
- spin_unlock_irqrestore(&cs->lock, flags);
- break;
- case (HW_DEACTIVATE | RESPONSE):
- skb_queue_purge(&cs->rq);
- skb_queue_purge(&cs->sq);
- if (cs->tx_skb) {
- dev_kfree_skb_any(cs->tx_skb);
- cs->tx_skb = NULL;
+ cs->writeisac(cs, ICC_ADF1, 0xa);
}
- if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
- del_timer(&cs->dbusytimer);
- if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
- schedule_event(cs, D_CLEARBUSY);
- break;
- default:
- if (cs->debug & L1_DEB_WARN)
- debugl1(cs, "icc_l1hw unknown %04x", pr);
- break;
+ } else {
+ /* IOM 2 Mode */
+ cs->writeisac(cs, ICC_SPCR, val);
+ if (val)
+ cs->writeisac(cs, ICC_ADF1, 0x8);
+ else
+ cs->writeisac(cs, ICC_ADF1, 0x0);
+ }
+ spin_unlock_irqrestore(&cs->lock, flags);
+ break;
+ case (HW_DEACTIVATE | RESPONSE):
+ skb_queue_purge(&cs->rq);
+ skb_queue_purge(&cs->sq);
+ if (cs->tx_skb) {
+ dev_kfree_skb_any(cs->tx_skb);
+ cs->tx_skb = NULL;
+ }
+ if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
+ del_timer(&cs->dbusytimer);
+ if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
+ schedule_event(cs, D_CLEARBUSY);
+ break;
+ default:
+ if (cs->debug & L1_DEB_WARN)
+ debugl1(cs, "icc_l1hw unknown %04x", pr);
+ break;
}
}
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
rbch = cs->readisac(cs, ICC_RBCH);
star = cs->readisac(cs, ICC_STAR);
- if (cs->debug)
+ if (cs->debug)
debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
rbch, star);
if (rbch & ICC_RBCH_XAC) { /* D-Channel Busy */
cs->DC_Close = DC_Close_icc;
cs->dc.icc.mon_tx = NULL;
cs->dc.icc.mon_rx = NULL;
- cs->writeisac(cs, ICC_MASK, 0xff);
- cs->dc.icc.mocr = 0xaa;
+ cs->writeisac(cs, ICC_MASK, 0xff);
+ cs->dc.icc.mocr = 0xaa;
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
/* IOM 1 Mode */
cs->writeisac(cs, ICC_ADF2, 0x0);
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