* Written by: Michael Chan (mchan@broadcom.com)
*/
+#include <linux/config.h>
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/delay.h>
+#include <asm/byteorder.h>
+#include <linux/time.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#ifdef NETIF_F_HW_VLAN_TX
+#include <linux/if_vlan.h>
+#define BCM_VLAN 1
+#endif
+#ifdef NETIF_F_TSO
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/checksum.h>
+#define BCM_TSO 1
+#endif
+#include <linux/workqueue.h>
+#include <linux/crc32.h>
+#include <linux/prefetch.h>
+#include <linux/cache.h>
+
#include "bnx2.h"
#include "bnx2_fw.h"
#define DRV_MODULE_NAME "bnx2"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "1.4.31"
-#define DRV_MODULE_RELDATE "January 19, 2006"
+#define DRV_MODULE_VERSION "1.4.39"
+#define DRV_MODULE_RELDATE "March 22, 2006"
#define RUN_AT(x) (jiffies + (x))
/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT (5*HZ)
-static char version[] __devinitdata =
+static const char version[] __devinitdata =
"Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
static void
bnx2_enable_int(struct bnx2 *bp)
{
- u32 val;
-
REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
- val = REG_RD(bp, BNX2_HC_COMMAND);
- REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+ REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
}
static void
static void
bnx2_free_mem(struct bnx2 *bp)
{
- if (bp->stats_blk) {
- pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
- bp->stats_blk, bp->stats_blk_mapping);
- bp->stats_blk = NULL;
- }
+ int i;
+
if (bp->status_blk) {
- pci_free_consistent(bp->pdev, sizeof(struct status_block),
+ pci_free_consistent(bp->pdev, bp->status_stats_size,
bp->status_blk, bp->status_blk_mapping);
bp->status_blk = NULL;
+ bp->stats_blk = NULL;
}
if (bp->tx_desc_ring) {
pci_free_consistent(bp->pdev,
}
kfree(bp->tx_buf_ring);
bp->tx_buf_ring = NULL;
- if (bp->rx_desc_ring) {
- pci_free_consistent(bp->pdev,
- sizeof(struct rx_bd) * RX_DESC_CNT,
- bp->rx_desc_ring, bp->rx_desc_mapping);
- bp->rx_desc_ring = NULL;
- }
- kfree(bp->rx_buf_ring);
+ for (i = 0; i < bp->rx_max_ring; i++) {
+ if (bp->rx_desc_ring[i])
+ pci_free_consistent(bp->pdev,
+ sizeof(struct rx_bd) * RX_DESC_CNT,
+ bp->rx_desc_ring[i],
+ bp->rx_desc_mapping[i]);
+ bp->rx_desc_ring[i] = NULL;
+ }
+ vfree(bp->rx_buf_ring);
bp->rx_buf_ring = NULL;
}
static int
bnx2_alloc_mem(struct bnx2 *bp)
{
- bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
- GFP_KERNEL);
+ int i, status_blk_size;
+
+ bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
+ GFP_KERNEL);
if (bp->tx_buf_ring == NULL)
return -ENOMEM;
- memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
sizeof(struct tx_bd) *
TX_DESC_CNT,
if (bp->tx_desc_ring == NULL)
goto alloc_mem_err;
- bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
- GFP_KERNEL);
+ bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
+ bp->rx_max_ring);
if (bp->rx_buf_ring == NULL)
goto alloc_mem_err;
- memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
- bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
- sizeof(struct rx_bd) *
- RX_DESC_CNT,
- &bp->rx_desc_mapping);
- if (bp->rx_desc_ring == NULL)
- goto alloc_mem_err;
+ memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
+ bp->rx_max_ring);
+
+ for (i = 0; i < bp->rx_max_ring; i++) {
+ bp->rx_desc_ring[i] =
+ pci_alloc_consistent(bp->pdev,
+ sizeof(struct rx_bd) * RX_DESC_CNT,
+ &bp->rx_desc_mapping[i]);
+ if (bp->rx_desc_ring[i] == NULL)
+ goto alloc_mem_err;
+
+ }
- bp->status_blk = pci_alloc_consistent(bp->pdev,
- sizeof(struct status_block),
+ /* Combine status and statistics blocks into one allocation. */
+ status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
+ bp->status_stats_size = status_blk_size +
+ sizeof(struct statistics_block);
+
+ bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
&bp->status_blk_mapping);
if (bp->status_blk == NULL)
goto alloc_mem_err;
- memset(bp->status_blk, 0, sizeof(struct status_block));
+ memset(bp->status_blk, 0, bp->status_stats_size);
- bp->stats_blk = pci_alloc_consistent(bp->pdev,
- sizeof(struct statistics_block),
- &bp->stats_blk_mapping);
- if (bp->stats_blk == NULL)
- goto alloc_mem_err;
+ bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
+ status_blk_size);
- memset(bp->stats_blk, 0, sizeof(struct statistics_block));
+ bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
return 0;
struct sk_buff *skb;
struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
dma_addr_t mapping;
- struct rx_bd *rxbd = &bp->rx_desc_ring[index];
+ struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
unsigned long align;
skb = dev_alloc_skb(bp->rx_buf_size);
bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
u16 cons, u16 prod)
{
- struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
- struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
- struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
- struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
+ struct sw_bd *cons_rx_buf, *prod_rx_buf;
+ struct rx_bd *cons_bd, *prod_bd;
+
+ cons_rx_buf = &bp->rx_buf_ring[cons];
+ prod_rx_buf = &bp->rx_buf_ring[prod];
pci_dma_sync_single_for_device(bp->pdev,
pci_unmap_addr(cons_rx_buf, mapping),
bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
- prod_rx_buf->skb = cons_rx_buf->skb;
- pci_unmap_addr_set(prod_rx_buf, mapping,
- pci_unmap_addr(cons_rx_buf, mapping));
+ bp->rx_prod_bseq += bp->rx_buf_use_size;
- memcpy(prod_bd, cons_bd, 8);
+ prod_rx_buf->skb = skb;
- bp->rx_prod_bseq += bp->rx_buf_use_size;
+ if (cons == prod)
+ return;
+ pci_unmap_addr_set(prod_rx_buf, mapping,
+ pci_unmap_addr(cons_rx_buf, mapping));
+
+ cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
+ prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
+ prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
+ prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
}
static int
u32 status;
struct sw_bd *rx_buf;
struct sk_buff *skb;
+ dma_addr_t dma_addr;
sw_ring_cons = RX_RING_IDX(sw_cons);
sw_ring_prod = RX_RING_IDX(sw_prod);
rx_buf = &bp->rx_buf_ring[sw_ring_cons];
skb = rx_buf->skb;
- pci_dma_sync_single_for_cpu(bp->pdev,
- pci_unmap_addr(rx_buf, mapping),
+
+ rx_buf->skb = NULL;
+
+ dma_addr = pci_unmap_addr(rx_buf, mapping);
+
+ pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
rx_hdr = (struct l2_fhdr *) skb->data;
skb = new_skb;
}
else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
- pci_unmap_single(bp->pdev,
- pci_unmap_addr(rx_buf, mapping),
+ pci_unmap_single(bp->pdev, dma_addr,
bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
skb_reserve(skb, bp->rx_offset);
rx_pkt++;
next_rx:
- rx_buf->skb = NULL;
-
sw_cons = NEXT_RX_BD(sw_cons);
sw_prod = NEXT_RX_BD(sw_prod);
spin_lock(&bp->phy_lock);
bnx2_phy_int(bp);
spin_unlock(&bp->phy_lock);
+
+ /* This is needed to take care of transient status
+ * during link changes.
+ */
+ REG_WR(bp, BNX2_HC_COMMAND,
+ bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+ REG_RD(bp, BNX2_HC_COMMAND);
}
if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
udelay(20);
+ bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
+
return rc;
}
bp->hw_rx_cons = 0;
bp->rx_prod_bseq = 0;
- rxbd = &bp->rx_desc_ring[0];
- for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
- rxbd->rx_bd_len = bp->rx_buf_use_size;
- rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
- }
+ for (i = 0; i < bp->rx_max_ring; i++) {
+ int j;
- rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
- rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
+ rxbd = &bp->rx_desc_ring[i][0];
+ for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
+ rxbd->rx_bd_len = bp->rx_buf_use_size;
+ rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
+ }
+ if (i == (bp->rx_max_ring - 1))
+ j = 0;
+ else
+ j = i + 1;
+ rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
+ rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
+ 0xffffffff;
+ }
val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
val |= 0x02 << 8;
CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
- val = (u64) bp->rx_desc_mapping >> 32;
+ val = (u64) bp->rx_desc_mapping[0] >> 32;
CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
- val = (u64) bp->rx_desc_mapping & 0xffffffff;
+ val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
- for ( ;ring_prod < bp->rx_ring_size; ) {
+ for (i = 0; i < bp->rx_ring_size; i++) {
if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
break;
}
REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
}
+static void
+bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
+{
+ u32 num_rings, max;
+
+ bp->rx_ring_size = size;
+ num_rings = 1;
+ while (size > MAX_RX_DESC_CNT) {
+ size -= MAX_RX_DESC_CNT;
+ num_rings++;
+ }
+ /* round to next power of 2 */
+ max = MAX_RX_RINGS;
+ while ((max & num_rings) == 0)
+ max >>= 1;
+
+ if (num_rings != max)
+ max <<= 1;
+
+ bp->rx_max_ring = max;
+ bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
+}
+
static void
bnx2_free_tx_skbs(struct bnx2 *bp)
{
if (bp->rx_buf_ring == NULL)
return;
- for (i = 0; i < RX_DESC_CNT; i++) {
+ for (i = 0; i < bp->rx_max_ring_idx; i++) {
struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
struct sk_buff *skb = rx_buf->skb;
struct sk_buff *skb, *rx_skb;
unsigned char *packet;
u16 rx_start_idx, rx_idx;
- u32 val;
dma_addr_t map;
struct tx_bd *txbd;
struct sw_bd *rx_buf;
map = pci_map_single(bp->pdev, skb->data, pkt_size,
PCI_DMA_TODEVICE);
- val = REG_RD(bp, BNX2_HC_COMMAND);
- REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+ REG_WR(bp, BNX2_HC_COMMAND,
+ bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+
REG_RD(bp, BNX2_HC_COMMAND);
udelay(5);
udelay(100);
- val = REG_RD(bp, BNX2_HC_COMMAND);
- REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+ REG_WR(bp, BNX2_HC_COMMAND,
+ bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+
REG_RD(bp, BNX2_HC_COMMAND);
udelay(5);
bnx2_test_intr(struct bnx2 *bp)
{
int i;
- u32 val;
u16 status_idx;
if (!netif_running(bp->dev))
status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
/* This register is not touched during run-time. */
- val = REG_RD(bp, BNX2_HC_COMMAND);
- REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+ REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
REG_RD(bp, BNX2_HC_COMMAND);
for (i = 0; i < 10; i++) {
{
struct bnx2 *bp = netdev_priv(dev);
- ering->rx_max_pending = MAX_RX_DESC_CNT;
+ ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
ering->rx_mini_max_pending = 0;
ering->rx_jumbo_max_pending = 0;
{
struct bnx2 *bp = netdev_priv(dev);
- if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
+ if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
(ering->tx_pending > MAX_TX_DESC_CNT) ||
(ering->tx_pending <= MAX_SKB_FRAGS)) {
return -EINVAL;
}
- bp->rx_ring_size = ering->rx_pending;
+ if (netif_running(bp->dev)) {
+ bnx2_netif_stop(bp);
+ bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
+ bnx2_free_skbs(bp);
+ bnx2_free_mem(bp);
+ }
+
+ bnx2_set_rx_ring_size(bp, ering->rx_pending);
bp->tx_ring_size = ering->tx_pending;
if (netif_running(bp->dev)) {
- bnx2_netif_stop(bp);
+ int rc;
+
+ rc = bnx2_alloc_mem(bp);
+ if (rc)
+ return rc;
bnx2_init_nic(bp);
bnx2_netif_start(bp);
}
bp->mac_addr[5] = (u8) reg;
bp->tx_ring_size = MAX_TX_DESC_CNT;
- bp->rx_ring_size = 100;
+ bnx2_set_rx_ring_size(bp, 100);
bp->rx_csum = 1;
if (!netif_running(dev))
return 0;
+ flush_scheduled_work();
bnx2_netif_stop(bp);
netif_device_detach(dev);
del_timer_sync(&bp->timer);
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