Pull mca-cleanup into release branch

[cascardo/linux.git] / drivers / net / bnx2.h

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 4a2e6ba..9f691cb 100644 (file)
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -1,6 +1,6 @@
 /* bnx2.h: Broadcom NX2 network driver.
  *
- * Copyright (c) 2004, 2005 Broadcom Corporation
+ * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -277,19 +277,7 @@ struct statistics_block {
  *  l2_fhdr definition
  */
 struct l2_fhdr {
-#if defined(__BIG_ENDIAN)
-       u16 l2_fhdr_errors;
-       u16 l2_fhdr_status;
-#elif defined(__LITTLE_ENDIAN)
-       u16 l2_fhdr_status;
-       u16 l2_fhdr_errors;
-#endif
-               #define L2_FHDR_ERRORS_BAD_CRC          (1<<1)
-               #define L2_FHDR_ERRORS_PHY_DECODE       (1<<2)
-               #define L2_FHDR_ERRORS_ALIGNMENT        (1<<3)
-               #define L2_FHDR_ERRORS_TOO_SHORT        (1<<4)
-               #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<5)
-
+       u32 l2_fhdr_status;
                #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
                #define L2_FHDR_STATUS_RULE_P2          (1<<3)
                #define L2_FHDR_STATUS_RULE_P3          (1<<4)
@@ -301,6 +289,14 @@ struct l2_fhdr {
                #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
                #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
 
+               #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
+               #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
+               #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
+               #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
+               #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
+               #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
+               #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
+
        u32 l2_fhdr_hash;
 #if defined(__BIG_ENDIAN)
        u16 l2_fhdr_pkt_len;
@@ -3715,6 +3711,15 @@ struct l2_fhdr {
 #define BNX2_MCP_ROM                                   0x00150000
 #define BNX2_MCP_SCRATCH                               0x00160000
 
+#define BNX2_SHM_HDR_SIGNATURE                         BNX2_MCP_SCRATCH
+#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK                         0xffff0000
+#define BNX2_SHM_HDR_SIGNATURE_SIG                      0x53530000
+#define BNX2_SHM_HDR_SIGNATURE_VER_MASK                         0x000000ff
+#define BNX2_SHM_HDR_SIGNATURE_VER_ONE                  0x00000001
+
+#define BNX2_SHM_HDR_ADDR_0                            BNX2_MCP_SCRATCH + 4
+#define BNX2_SHM_HDR_ADDR_1                            BNX2_MCP_SCRATCH + 8
+
 
 #define NUM_MC_HASH_REGISTERS   8
 
@@ -3905,6 +3910,9 @@ struct bnx2 {
        u16                     tx_cons;
        int                     tx_ring_size;
 
+       u16                     hw_tx_cons;
+       u16                     hw_rx_cons;
+
 #ifdef BCM_VLAN 
        struct                  vlan_group *vlgrp;
 #endif
@@ -3944,6 +3952,7 @@ struct bnx2 {
 #define NO_WOL_FLAG                    8
 #define USING_DAC_FLAG                 0x10
 #define USING_MSI_FLAG                 0x20
+#define ASF_ENABLE_FLAG                        0x40
 
        u32                     phy_flags;
 #define PHY_SERDES_FLAG                        1
@@ -3974,6 +3983,7 @@ struct bnx2 {
 #define CHIP_ID_5706_A2                        0x57060020
 #define CHIP_ID_5708_A0                        0x57080000
 #define CHIP_ID_5708_B0                        0x57081000
+#define CHIP_ID_5708_B1                        0x57081010
 
 #define CHIP_BOND_ID(bp)               (((bp)->chip_id) & 0xf)
 
@@ -3986,7 +3996,7 @@ struct bnx2 {
        u16                     bus_speed_mhz;
        u8                      wol;
 
-       u8                      fw_timed_out;
+       u8                      pad;
 
        u16                     fw_wr_seq;
        u16                     fw_drv_pulse_wr_seq;
@@ -4052,6 +4062,8 @@ struct bnx2 {
 
        u8                      mac_addr[8];
 
+       u32                     shmem_base;
+
        u32                     fw_ver;
 
        int                     pm_cap;
@@ -4060,6 +4072,7 @@ struct bnx2 {
        struct net_device_stats net_stats;
 
        struct flash_spec       *flash_info;
+       u32                     flash_size;
 };
 
 static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
@@ -4158,7 +4171,7 @@ struct fw_info {
  * the firmware has timed out, the driver will assume there is no firmware
  * running and there won't be any firmware-driver synchronization during a
  * driver reset. */
-#define FW_ACK_TIME_OUT_MS                  50
+#define FW_ACK_TIME_OUT_MS                  100
 
 
 #define BNX2_DRV_RESET_SIGNATURE               0x00000000
@@ -4191,6 +4204,38 @@ struct fw_info {
 #define BNX2_FW_MSG_STATUS_FAILURE              0x00ff0000
 
 #define BNX2_LINK_STATUS                       0x0000000c
+#define BNX2_LINK_STATUS_INIT_VALUE             0xffffffff 
+#define BNX2_LINK_STATUS_LINK_UP                0x1 
+#define BNX2_LINK_STATUS_LINK_DOWN              0x0 
+#define BNX2_LINK_STATUS_SPEED_MASK             0x1e
+#define BNX2_LINK_STATUS_AN_INCOMPLETE          (0<<1) 
+#define BNX2_LINK_STATUS_10HALF                         (1<<1) 
+#define BNX2_LINK_STATUS_10FULL                         (2<<1) 
+#define BNX2_LINK_STATUS_100HALF                (3<<1) 
+#define BNX2_LINK_STATUS_100BASE_T4             (4<<1) 
+#define BNX2_LINK_STATUS_100FULL                (5<<1) 
+#define BNX2_LINK_STATUS_1000HALF               (6<<1) 
+#define BNX2_LINK_STATUS_1000FULL               (7<<1) 
+#define BNX2_LINK_STATUS_2500HALF               (8<<1) 
+#define BNX2_LINK_STATUS_2500FULL               (9<<1) 
+#define BNX2_LINK_STATUS_AN_ENABLED             (1<<5) 
+#define BNX2_LINK_STATUS_AN_COMPLETE            (1<<6) 
+#define BNX2_LINK_STATUS_PARALLEL_DET           (1<<7) 
+#define BNX2_LINK_STATUS_RESERVED               (1<<8) 
+#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL    (1<<9) 
+#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF    (1<<10) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100BT4      (1<<11) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100FULL     (1<<12) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100HALF     (1<<13) 
+#define BNX2_LINK_STATUS_PARTNER_AD_10FULL      (1<<14) 
+#define BNX2_LINK_STATUS_PARTNER_AD_10HALF      (1<<15) 
+#define BNX2_LINK_STATUS_TX_FC_ENABLED          (1<<16) 
+#define BNX2_LINK_STATUS_RX_FC_ENABLED          (1<<17) 
+#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP  (1<<18) 
+#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP         (1<<19) 
+#define BNX2_LINK_STATUS_SERDES_LINK            (1<<20) 
+#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL    (1<<21) 
+#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF    (1<<22) 
 
 #define BNX2_DRV_PULSE_MB                      0x00000010
 #define BNX2_DRV_PULSE_SEQ_MASK                         0x00007fff
@@ -4229,6 +4274,9 @@ struct fw_info {
 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1       0x100
 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2       0x200
 
+#define BNX2_SHARED_HW_CFG_CONFIG2             0x00000040
+#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK       0x00fff000
+
 #define BNX2_DEV_INFO_BC_REV                   0x0000004c
 
 #define BNX2_PORT_HW_CFG_MAC_UPPER             0x00000050