Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...

[cascardo/linux.git] / drivers / net / bnx2x_main.c

diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index a2de0cd..2d035d7 100644 (file)
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -56,8 +56,8 @@
 #include "bnx2x_init_ops.h"
 #include "bnx2x_dump.h"
 
-#define DRV_MODULE_VERSION     "1.48.113-1"
-#define DRV_MODULE_RELDATE     "2009/07/21"
+#define DRV_MODULE_VERSION     "1.48.114-1"
+#define DRV_MODULE_RELDATE     "2009/07/29"
 #define BNX2X_BC_VER           0x040200
 
 #include <linux/firmware.h>
@@ -4831,7 +4831,14 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
        int mode = bp->rx_mode;
        int mask = (1 << BP_L_ID(bp));
        int func = BP_FUNC(bp);
+       int port = BP_PORT(bp);
        int i;
+       /* All but management unicast packets should pass to the host as well */
+       u32 llh_mask =
+               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
+               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
+               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
+               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
 
        DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
 
@@ -4855,6 +4862,8 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
                tstorm_mac_filter.ucast_accept_all = mask;
                tstorm_mac_filter.mcast_accept_all = mask;
                tstorm_mac_filter.bcast_accept_all = mask;
+               /* pass management unicast packets as well */
+               llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
                break;
 
        default:
@@ -4862,6 +4871,10 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
                break;
        }
 
+       REG_WR(bp,
+              (port ? NIG_REG_LLH1_BRB1_DRV_MASK : NIG_REG_LLH0_BRB1_DRV_MASK),
+              llh_mask);
+
        for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
                REG_WR(bp, BAR_TSTRORM_INTMEM +
                       TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
@@ -7341,17 +7354,17 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
 
                for (i = 0; i < MC_HASH_SIZE; i++)
                        REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
+
+               REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
        }
 
        if (unload_mode == UNLOAD_NORMAL)
                reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
 
-       else if (bp->flags & NO_WOL_FLAG) {
+       else if (bp->flags & NO_WOL_FLAG)
                reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
-               if (CHIP_IS_E1H(bp))
-                       REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
 
-       } else if (bp->wol) {
+       else if (bp->wol) {
                u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
                u8 *mac_addr = bp->dev->dev_addr;
                u32 val;
@@ -9402,10 +9415,9 @@ static int bnx2x_test_registers(struct bnx2x *bp)
                { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
                { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
                { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
-               { NIG_REG_EGRESS_MNG0_FIFO,           20, 0xffffffff },
                { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
-/* 20 */       { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
-               { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
+               { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
+/* 20 */       { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
                { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
                { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
                { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
@@ -9414,8 +9426,8 @@ static int bnx2x_test_registers(struct bnx2x *bp)
                { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
                { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
                { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
-/* 30 */       { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
-               { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
+               { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
+/* 30 */       { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
                { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
                { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
                { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },