#define RX_BCST_EN (1 << 2)
#define RX_MCST_EN (1 << 3)
#define RX_UCST_EN (1 << 4)
-#define G_MISTP_STATE_SHIFT 5
-#define G_MISTP_NO_STP (0 << G_MISTP_STATE_SHIFT)
-#define G_MISTP_DIS_STATE (1 << G_MISTP_STATE_SHIFT)
-#define G_MISTP_BLOCK_STATE (2 << G_MISTP_STATE_SHIFT)
-#define G_MISTP_LISTEN_STATE (3 << G_MISTP_STATE_SHIFT)
-#define G_MISTP_LEARN_STATE (4 << G_MISTP_STATE_SHIFT)
-#define G_MISTP_FWD_STATE (5 << G_MISTP_STATE_SHIFT)
-#define G_MISTP_STATE_MASK 0x7
#define CORE_SWMODE 0x0002c
#define SW_FWDG_MODE (1 << 0)
#define BRCM_HDR_EN_P5 (1 << 1)
#define BRCM_HDR_EN_P7 (1 << 2)
-#define CORE_BRCM_HDR_CTRL2 0x0828
-
-#define CORE_HL_PRTC_CTRL 0x0940
-#define ARP_EN (1 << 0)
-#define RARP_EN (1 << 1)
-#define DHCP_EN (1 << 2)
-#define ICMPV4_EN (1 << 3)
-#define ICMPV6_EN (1 << 4)
-#define ICMPV6_FWD_MODE (1 << 5)
-#define IGMP_DIP_EN (1 << 8)
-#define IGMP_RPTLVE_EN (1 << 9)
-#define IGMP_RTPLVE_FWD_MODE (1 << 10)
-#define IGMP_QRY_EN (1 << 11)
-#define IGMP_QRY_FWD_MODE (1 << 12)
-#define IGMP_UKN_EN (1 << 13)
-#define IGMP_UKN_FWD_MODE (1 << 14)
-#define MLD_RPTDONE_EN (1 << 15)
-#define MLD_RPTDONE_FWD_MODE (1 << 16)
-#define MLD_QRY_EN (1 << 17)
-#define MLD_QRY_FWD_MODE (1 << 18)
-
#define CORE_RST_MIB_CNT_EN 0x0950
#define CORE_BRCM_HDR_RX_DIS 0x0980
#define CORE_BRCM_HDR_TX_DIS 0x0988
-#define CORE_ARLA_NUM_ENTRIES 1024
-
-#define CORE_ARLA_RWCTL 0x1400
-#define ARL_RW (1 << 0)
-#define IVL_SVL_SELECT (1 << 6)
-#define ARL_STRTDN (1 << 7)
-
-#define CORE_ARLA_MAC 0x1408
-#define CORE_ARLA_VID 0x1420
-#define ARLA_VIDTAB_INDX_MASK 0x1fff
-
-#define CORE_ARLA_MACVID0 0x1440
-#define MAC_MASK 0xffffffffff
-#define VID_SHIFT 48
-#define VID_MASK 0xfff
-
-#define CORE_ARLA_FWD_ENTRY0 0x1460
-#define PORTID_MASK 0x1ff
-#define ARL_CON_SHIFT 9
-#define ARL_CON_MASK 0x3
-#define ARL_PRI_SHIFT 11
-#define ARL_PRI_MASK 0x7
-#define ARL_AGE (1 << 14)
-#define ARL_STATIC (1 << 15)
-#define ARL_VALID (1 << 16)
-
-#define CORE_ARLA_MACVID_ENTRY(x) (CORE_ARLA_MACVID0 + ((x) * 0x40))
-#define CORE_ARLA_FWD_ENTRY(x) (CORE_ARLA_FWD_ENTRY0 + ((x) * 0x40))
-
-#define CORE_ARLA_SRCH_CTL 0x1540
-#define ARLA_SRCH_VLID (1 << 0)
-#define IVL_SVL_SELECT (1 << 6)
-#define ARLA_SRCH_STDN (1 << 7)
-
-#define CORE_ARLA_SRCH_ADR 0x1544
-#define ARLA_SRCH_ADR_VALID (1 << 15)
-
-#define CORE_ARLA_SRCH_RSLT_0_MACVID 0x1580
-#define CORE_ARLA_SRCH_RSLT_0 0x15a0
-
-#define CORE_ARLA_SRCH_RSLT_MACVID(x) (CORE_ARLA_SRCH_RSLT_0_MACVID + ((x) * 0x40))
-#define CORE_ARLA_SRCH_RSLT(x) (CORE_ARLA_SRCH_RSLT_0 + ((x) * 0x40))
-
#define CORE_ARLA_VTBL_RWCTRL 0x1600
#define ARLA_VTBL_CMD_WRITE 0
#define ARLA_VTBL_CMD_READ 1
#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
((x) * P_TXQ_PSM_VDD_SHIFT))
-#define CORE_P0_MIB_OFFSET 0x8000
-#define P_MIB_SIZE 0x400
-#define CORE_P_MIB_OFFSET(x) (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
-
#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
#define PORT_VLAN_CTRL_MASK 0x1ff
-#define CORE_VLAN_CTRL0 0xd000
-#define CHANGE_1P_VID_INNER (1 << 0)
-#define CHANGE_1P_VID_OUTER (1 << 1)
-#define CHANGE_1Q_VID (1 << 3)
-#define VLAN_LEARN_MODE_SVL (0 << 5)
-#define VLAN_LEARN_MODE_IVL (3 << 5)
-#define VLAN_EN (1 << 7)
-
-#define CORE_VLAN_CTRL1 0xd004
-#define EN_RSV_MCAST_FWDMAP (1 << 2)
-#define EN_RSV_MCAST_UNTAG (1 << 3)
-#define EN_IPMC_BYPASS_FWDMAP (1 << 5)
-#define EN_IPMC_BYPASS_UNTAG (1 << 6)
-
-#define CORE_VLAN_CTRL2 0xd008
-#define EN_MIIM_BYPASS_V_FWDMAP (1 << 2)
-#define EN_GMRP_GVRP_V_FWDMAP (1 << 5)
-#define EN_GMRP_GVRP_UNTAG_MAP (1 << 6)
-
-#define CORE_VLAN_CTRL3 0xd00c
-#define EN_DROP_NON1Q_MASK 0x1ff
-
-#define CORE_VLAN_CTRL4 0xd014
-#define RESV_MCAST_FLOOD (1 << 1)
-#define EN_DOUBLE_TAG_MASK 0x3
-#define EN_DOUBLE_TAG_SHIFT 2
-#define EN_MGE_REV_GMRP (1 << 4)
-#define EN_MGE_REV_GVRP (1 << 5)
-#define INGR_VID_CHK_SHIFT 6
-#define INGR_VID_CHK_MASK 0x3
-#define INGR_VID_CHK_FWD (0 << INGR_VID_CHK_SHIFT)
-#define INGR_VID_CHK_DROP (1 << INGR_VID_CHK_SHIFT)
-#define INGR_VID_CHK_NO_CHK (2 << INGR_VID_CHK_SHIFT)
-#define INGR_VID_CHK_VID_VIOL_IMP (3 << INGR_VID_CHK_SHIFT)
-
-#define CORE_VLAN_CTRL5 0xd018
-#define EN_CPU_RX_BYP_INNER_CRCCHCK (1 << 0)
-#define EN_VID_FFF_FWD (1 << 2)
-#define DROP_VTABLE_MISS (1 << 3)
-#define EGRESS_DIR_FRM_BYP_TRUNK_EN (1 << 4)
-#define PRESV_NON1Q (1 << 6)
-
-#define CORE_VLAN_CTRL6 0xd01c
-#define STRICT_SFD_DETECT (1 << 0)
-#define DIS_ARL_BUST_LMIT (1 << 4)
-
#define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
#define CFI_SHIFT 12
#define PRI_SHIFT 13
projects / cascardo / linux.git / blobdiff