cxgb4: Add support for dynamic allocation of resources for ULD

[cascardo/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_uld.h

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
index cf711d5..ab40372 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
@@ -32,8 +32,8 @@
  * SOFTWARE.
  */
 
-#ifndef __CXGB4_OFLD_H
-#define __CXGB4_OFLD_H
+#ifndef __CXGB4_ULD_H
+#define __CXGB4_ULD_H
 
 #include <linux/cache.h>
 #include <linux/spinlock.h>
@@ -191,6 +191,7 @@ static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue)
 enum cxgb4_uld {
        CXGB4_ULD_RDMA,
        CXGB4_ULD_ISCSI,
+       CXGB4_ULD_ISCSIT,
        CXGB4_ULD_MAX
 };
 
@@ -212,6 +213,7 @@ struct l2t_data;
 struct net_device;
 struct pkt_gl;
 struct tp_tcp_stats;
+struct t4_lro_mgr;
 
 struct cxgb4_range {
        unsigned int start;
@@ -273,6 +275,10 @@ struct cxgb4_lld_info {
        unsigned int max_ordird_qp;          /* Max ORD/IRD depth per RDMA QP */
        unsigned int max_ird_adapter;        /* Max IRD memory per adapter */
        bool ulptx_memwrite_dsgl;            /* use of T5 DSGL allowed */
+       unsigned int iscsi_tagmask;          /* iscsi ddp tag mask */
+       unsigned int iscsi_pgsz_order;       /* iscsi ddp page size orders */
+       unsigned int iscsi_llimit;           /* chip's iscsi region llimit */
+       void **iscsi_ppm;                    /* iscsi page pod manager */
        int nodeid;                          /* device numa node id */
 };
 
@@ -283,10 +289,43 @@ struct cxgb4_uld_info {
                          const struct pkt_gl *gl);
        int (*state_change)(void *handle, enum cxgb4_state new_state);
        int (*control)(void *handle, enum cxgb4_control control, ...);
+       int (*lro_rx_handler)(void *handle, const __be64 *rsp,
+                             const struct pkt_gl *gl,
+                             struct t4_lro_mgr *lro_mgr,
+                             struct napi_struct *napi);
+       void (*lro_flush)(struct t4_lro_mgr *);
+};
+
+enum cxgb4_pci_uld {
+       CXGB4_PCI_ULD1,
+       CXGB4_PCI_ULD_MAX
+};
+
+struct cxgb4_pci_uld_info {
+       const char *name;
+       bool lro;
+       void *handle;
+       unsigned int nrxq;
+       unsigned int nciq;
+       unsigned int rxq_size;
+       unsigned int ciq_size;
+       void *(*add)(const struct cxgb4_lld_info *p);
+       int (*rx_handler)(void *handle, const __be64 *rsp,
+                         const struct pkt_gl *gl);
+       int (*state_change)(void *handle, enum cxgb4_state new_state);
+       int (*control)(void *handle, enum cxgb4_control control, ...);
+       int (*lro_rx_handler)(void *handle, const __be64 *rsp,
+                             const struct pkt_gl *gl,
+                             struct t4_lro_mgr *lro_mgr,
+                             struct napi_struct *napi);
+       void (*lro_flush)(struct t4_lro_mgr *);
 };
 
 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
 int cxgb4_unregister_uld(enum cxgb4_uld type);
+int cxgb4_register_pci_uld(enum cxgb4_pci_uld type,
+                          struct cxgb4_pci_uld_info *p);
+int cxgb4_unregister_pci_uld(enum cxgb4_pci_uld type);
 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb);
 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo);
 unsigned int cxgb4_port_chan(const struct net_device *dev);
@@ -319,4 +358,4 @@ int cxgb4_bar2_sge_qregs(struct net_device *dev,
                         u64 *pbar2_qoffset,
                         unsigned int *pbar2_qid);
 
-#endif  /* !__CXGB4_OFLD_H */
+#endif  /* !__CXGB4_ULD_H */