ixgbe: Add definitions for x550em_a 10G MAC

[cascardo/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_type.h

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
index bf7367a..b505da3 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 10 Gigabit PCI Express Linux driver
-  Copyright(c) 1999 - 2015 Intel Corporation.
+  Copyright(c) 1999 - 2016 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -75,21 +75,24 @@
 #define IXGBE_DEV_ID_X540T1              0x1560
 
 #define IXGBE_DEV_ID_X550T             0x1563
+#define IXGBE_DEV_ID_X550T1            0x15D1
 #define IXGBE_DEV_ID_X550EM_X_KX4      0x15AA
 #define IXGBE_DEV_ID_X550EM_X_KR       0x15AB
 #define IXGBE_DEV_ID_X550EM_X_SFP      0x15AC
 #define IXGBE_DEV_ID_X550EM_X_10G_T    0x15AD
 #define IXGBE_DEV_ID_X550EM_X_1G_T     0x15AE
+#define IXGBE_DEV_ID_X550EM_A_SFP_N    0x15C4
+
+/* VF Device IDs */
 #define IXGBE_DEV_ID_X550_VF_HV        0x1564
 #define IXGBE_DEV_ID_X550_VF           0x1565
 #define IXGBE_DEV_ID_X550EM_X_VF       0x15A8
 #define IXGBE_DEV_ID_X550EM_X_VF_HV    0x15A9
-
-/* VF Device IDs */
 #define IXGBE_DEV_ID_82599_VF           0x10ED
 #define IXGBE_DEV_ID_X540_VF            0x1515
 #define IXGBE_DEV_ID_X550_VF           0x1565
 #define IXGBE_DEV_ID_X550EM_X_VF       0x15A8
+#define IXGBE_DEV_ID_X550EM_A_VF       0x15C5
 
 #define IXGBE_CAT(r, m)        IXGBE_##r##_##m
 
@@ -128,7 +131,7 @@
 #define IXGBE_FLA_X540         IXGBE_FLA_8259X
 #define IXGBE_FLA_X550         IXGBE_FLA_8259X
 #define IXGBE_FLA_X550EM_x     IXGBE_FLA_8259X
-#define IXGBE_FLA_X550EM_a     0x15F6C
+#define IXGBE_FLA_X550EM_a     0x15F68
 #define IXGBE_FLA(_hw)         IXGBE_BY_MAC((_hw), FLA)
 #define IXGBE_EEMNGCTL  0x10110
 #define IXGBE_EEMNGDATA 0x10114
@@ -143,13 +146,6 @@
 #define IXGBE_GRC_X550EM_a     0x15F64
 #define IXGBE_GRC(_hw)         IXGBE_BY_MAC((_hw), GRC)
 
-#define IXGBE_SRAMREL_8259X    0x10210
-#define IXGBE_SRAMREL_X540     IXGBE_SRAMREL_8259X
-#define IXGBE_SRAMREL_X550     IXGBE_SRAMREL_8259X
-#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL_8259X
-#define IXGBE_SRAMREL_X550EM_a 0x15F6C
-#define IXGBE_SRAMREL(_hw)     IXGBE_BY_MAC((_hw), SRAMREL)
-
 /* General Receive Control */
 #define IXGBE_GRC_MNG  0x00000001 /* Manageability Enable */
 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
@@ -375,6 +371,8 @@ struct ixgbe_thermal_sensor_data {
 #define IXGBE_MRCTL(_i)      (0x0F600 + ((_i) * 4))
 #define IXGBE_VMRVLAN(_i)    (0x0F610 + ((_i) * 4))
 #define IXGBE_VMRVM(_i)      (0x0F630 + ((_i) * 4))
+#define IXGBE_WQBR_RX(_i)    (0x2FB0 + ((_i) * 4)) /* 4 total */
+#define IXGBE_WQBR_TX(_i)    (0x8130 + ((_i) * 4)) /* 4 total */
 #define IXGBE_L34T_IMIR(_i)  (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 #define IXGBE_RXFECCERR0         0x051B8
 #define IXGBE_LLITHRESH 0x0EC90
@@ -446,6 +444,8 @@ struct ixgbe_thermal_sensor_data {
 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
+#define IXGBE_DMATXCTL_MDP_EN   0x20 /* Bit 5 */
+#define IXGBE_DMATXCTL_MBINTEN  0x40 /* Bit 6 */
 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 
 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
@@ -554,7 +554,6 @@ struct ixgbe_thermal_sensor_data {
 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 
-
 /* Security Control Registers */
 #define IXGBE_SECTXCTRL         0x08800
 #define IXGBE_SECTXSTAT         0x08804
@@ -1203,6 +1202,8 @@ struct ixgbe_thermal_sensor_data {
 #define IXGBE_RDRXCTL_RSCLLIDIS     0x00800000 /* Disable RSC compl on LLI */
 #define IXGBE_RDRXCTL_RSCACKC       0x02000000 /* must set 1 when RSC enabled */
 #define IXGBE_RDRXCTL_FCOE_WRFIX    0x04000000 /* must set 1 when RSC enabled */
+#define IXGBE_RDRXCTL_MBINTEN       0x10000000
+#define IXGBE_RDRXCTL_MDP_EN        0x20000000
 
 /* RQTC Bit Masks and Shifts */
 #define IXGBE_RQTC_SHIFT_TC(_i)     ((_i) * 4)
@@ -1957,7 +1958,9 @@ enum {
 #define IXGBE_GSSR_PHY1_SM             0x0004
 #define IXGBE_GSSR_MAC_CSR_SM          0x0008
 #define IXGBE_GSSR_FLASH_SM            0x0010
+#define IXGBE_GSSR_NVM_UPDATE_SM       0x0200
 #define IXGBE_GSSR_SW_MNG_SM           0x0400
+#define IXGBE_GSSR_TOKEN_SM    0x40000000 /* SW bit for shared access */
 #define IXGBE_GSSR_SHARED_I2C_SM       0x1806 /* Wait for both phys & I2Cs */
 #define IXGBE_GSSR_I2C_MASK            0x1800
 #define IXGBE_GSSR_NVM_PHY_MASK                0xF
@@ -2530,6 +2533,10 @@ enum ixgbe_fdir_pballoc_type {
 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
+#define IXGBE_FDIRCTRL_DROP_NO_MATCH           0x00008000
+#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT                21
+#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN      0x0001 /* bit 23:21, 001b */
+#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD                0x0002 /* bit 23:21, 010b */
 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
@@ -2948,7 +2955,6 @@ union ixgbe_atr_hash_dword {
        IXGBE_CAT(EEC, m),              \
        IXGBE_CAT(FLA, m),              \
        IXGBE_CAT(GRC, m),              \
-       IXGBE_CAT(SRAMREL, m),          \
        IXGBE_CAT(FACTPS, m),           \
        IXGBE_CAT(SWSM, m),             \
        IXGBE_CAT(SWFW_SYNC, m),        \
@@ -2989,6 +2995,7 @@ enum ixgbe_mac_type {
        ixgbe_mac_X540,
        ixgbe_mac_X550,
        ixgbe_mac_X550EM_x,
+       ixgbe_mac_x550em_a,
        ixgbe_num_macs
 };
 
@@ -3130,8 +3137,8 @@ struct ixgbe_bus_info {
        enum ixgbe_bus_width width;
        enum ixgbe_bus_type type;
 
-       u16 func;
-       u16 lan_id;
+       u8 func;
+       u8 lan_id;
 };
 
 /* Flow control parameters */
@@ -3266,6 +3273,7 @@ struct ixgbe_mac_operations {
        s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
        s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
        void (*release_swfw_sync)(struct ixgbe_hw *, u32);
+       void (*init_swfw_sync)(struct ixgbe_hw *);
        s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
        s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
 
@@ -3308,6 +3316,7 @@ struct ixgbe_mac_operations {
 
        /* Flow Control */
        s32 (*fc_enable)(struct ixgbe_hw *);
+       s32 (*setup_fc)(struct ixgbe_hw *);
 
        /* Manageability interface */
        s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
@@ -3442,7 +3451,7 @@ struct ixgbe_mbx_stats {
 };
 
 struct ixgbe_mbx_info {
-       struct ixgbe_mbx_operations ops;
+       const struct ixgbe_mbx_operations *ops;
        struct ixgbe_mbx_stats stats;
        u32 timeout;
        u32 usec_delay;
@@ -3475,10 +3484,10 @@ struct ixgbe_hw {
 struct ixgbe_info {
        enum ixgbe_mac_type             mac;
        s32                             (*get_invariants)(struct ixgbe_hw *);
-       struct ixgbe_mac_operations     *mac_ops;
-       struct ixgbe_eeprom_operations  *eeprom_ops;
-       struct ixgbe_phy_operations     *phy_ops;
-       struct ixgbe_mbx_operations     *mbx_ops;
+       const struct ixgbe_mac_operations       *mac_ops;
+       const struct ixgbe_eeprom_operations    *eeprom_ops;
+       const struct ixgbe_phy_operations       *phy_ops;
+       const struct ixgbe_mbx_operations       *mbx_ops;
        const u32                       *mvals;
 };
 
@@ -3525,6 +3534,7 @@ struct ixgbe_info {
 
 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
 #define IXGBE_KRM_LINK_CTRL_1(P)       ((P) ? 0x820C : 0x420C)
+#define IXGBE_KRM_AN_CNTL_1(P)         ((P) ? 0x822C : 0x422C)
 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)        ((P) ? 0x8B00 : 0x4B00)
@@ -3547,6 +3557,9 @@ struct ixgbe_info {
 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE           (1 << 29)
 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART          (1 << 31)
 
+#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE                  (1 << 28)
+#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE                  (1 << 29)
+
 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN                        (1 << 6)
 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN           (1 << 15)
 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN          (1 << 16)