ath5k: Misc fixes/cleanups

[cascardo/linux.git] / drivers / net / natsemi.c

diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 87cde06..900ab5d 100644 (file)
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -127,7 +127,7 @@ static int full_duplex[MAX_UNITS];
 #define NATSEMI_RX_LIMIT       2046    /* maximum supported by hardware */
 
 /* These identify the driver base version and may not be removed. */
-static const char version[] __devinitdata =
+static char version[] __devinitdata =
   KERN_INFO DRV_NAME " dp8381x driver, version "
       DRV_VERSION ", " DRV_RELDATE "\n"
   KERN_INFO "  originally by Donald Becker <becker@scyld.com>\n"
@@ -203,22 +203,8 @@ skbuff at an offset of "+2", 16-byte aligning the IP header.
 IIId. Synchronization
 
 Most operations are synchronized on the np->lock irq spinlock, except the
-performance critical codepaths:
-
-The rx process only runs in the interrupt handler. Access from outside
-the interrupt handler is only permitted after disable_irq().
-
-The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
-is set, then access is permitted under spin_lock_irq(&np->lock).
-
-Thus configuration functions that want to access everything must call
-       disable_irq(dev->irq);
-       netif_tx_lock_bh(dev);
-       spin_lock_irq(&np->lock);
-
-IV. Notes
-
-NatSemi PCI network controllers are very uncommon.
+recieve and transmit paths which are synchronised using a combination of
+hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
 
 IVb. References
 
@@ -252,7 +238,7 @@ enum {
 };
 
 /* array of board data directly indexed by pci_tbl[x].driver_data */
-static const struct {
+static struct {
        const char *name;
        unsigned long flags;
        unsigned int eeprom_size;
@@ -261,7 +247,7 @@ static const struct {
        { "NatSemi DP8381[56]", 0, 24 },
 };
 
-static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
+static struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
        { PCI_VENDOR_ID_NS, 0x0020, 0x12d9,     0x000c,     0, 0, 0 },
        { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
        { }     /* terminate list */
@@ -525,10 +511,10 @@ enum PhyCtrl_bits {
 /* Note that using only 32 bit fields simplifies conversion to big-endian
    architectures. */
 struct netdev_desc {
-       u32 next_desc;
-       s32 cmd_status;
-       u32 addr;
-       u32 software_use;
+       __le32 next_desc;
+       __le32 cmd_status;
+       __le32 addr;
+       __le32 software_use;
 };
 
 /* Bits in network_desc.status */
@@ -2032,7 +2018,7 @@ static void drain_rx(struct net_device *dev)
        /* Free all the skbuffs in the Rx queue. */
        for (i = 0; i < RX_RING_SIZE; i++) {
                np->rx_ring[i].cmd_status = 0;
-               np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
+               np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
                if (np->rx_skbuff[i]) {
                        pci_unmap_single(np->pci_dev,
                                np->rx_dma[i], buflen,
@@ -2266,7 +2252,7 @@ static int natsemi_poll(struct napi_struct *napi, int budget)
        /* Reenable interrupts providing nothing is trying to shut
         * the chip down. */
        spin_lock(&np->lock);
-       if (!np->hands_off && netif_running(dev))
+       if (!np->hands_off)
                natsemi_irq_enable(dev);
        spin_unlock(&np->lock);