CHROMIUMOS: Move ath recv hang messages behind a flag

[cascardo/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index bc992b2..60032b2 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -373,7 +373,7 @@ static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
                        else
                                spur_subchannel_sd = 0;
 
-                       spur_freq_sd = (freq_offset << 9) / 11;
+                       spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 
                } else {
                        if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
@@ -382,7 +382,7 @@ static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
                        else
                                spur_subchannel_sd = 1;
 
-                       spur_freq_sd = (freq_offset << 9) / 11;
+                       spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 
                }
 
@@ -694,7 +694,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
        ar9003_hw_override_ini(ah);
        ar9003_hw_set_channel_regs(ah, chan);
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
-       ath9k_hw_apply_txpower(ah, chan);
+       ath9k_hw_apply_txpower(ah, chan, false);
 
        if (AR_SREV_9462(ah)) {
                if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
@@ -1504,3 +1504,51 @@ void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
        REG_WRITE(ah, AR_PHY_RESTART, val);
 }
 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
+
+void ar9003_hw_dump_ani_reg(struct ath_hw *ah)
+{
+       u32 reg;
+       struct ath_common *common = ath9k_hw_common(ah);
+
+       reg = REG_READ(ah, AR_PHY_FIND_SIG_LOW);
+       ath_dbg(common, RX_STUCK, "FIRStep Low = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
+                       MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
+       reg = REG_READ(ah, AR_PHY_DESIRED_SZ);
+       ath_dbg(common, RX_STUCK, "Total Desired = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_DESIRED_SZ_TOT_DES),
+                       MS(reg, AR_PHY_DESIRED_SZ_TOT_DES));
+       ath_dbg(common, RX_STUCK, "ADC Desired = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_DESIRED_SZ_ADC),
+                       MS(reg, AR_PHY_DESIRED_SZ_ADC));
+       reg = REG_READ(ah, AR_PHY_FIND_SIG);
+       ath_dbg(common, RX_STUCK, "FIRStep = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_FIND_SIG_FIRSTEP),
+                       MS(reg, AR_PHY_FIND_SIG_FIRSTEP));
+       reg = REG_READ(ah, AR_PHY_AGC);
+       ath_dbg(common, RX_STUCK, "Coarse High = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_AGC_COARSE_HIGH),
+                       MS(reg, AR_PHY_AGC_COARSE_HIGH));
+       ath_dbg(common, RX_STUCK, "Coarse Low = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_AGC_COARSE_LOW),
+                       MS(reg, AR_PHY_AGC_COARSE_LOW));
+       ath_dbg(common, RX_STUCK, "Coarse Power Constant = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_AGC_COARSE_PWR_CONST),
+                       MS(reg, AR_PHY_AGC_COARSE_PWR_CONST));
+       reg = REG_READ(ah, AR_PHY_TIMING5);
+       ath_dbg(common, RX_STUCK, "Enable Cyclic Power Thresh = %d\n",
+                       MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE));
+       ath_dbg(common, RX_STUCK, "Cyclic Power Thresh = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_TIMING5_CYCPWR_THR1),
+                       MS(reg, AR_PHY_TIMING5_CYCPWR_THR1));
+       ath_dbg(common, RX_STUCK, "Cyclic Power Thresh 1A= 0x%x (%d)\n",
+                       MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A),
+                       MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A));
+       reg = REG_READ(ah, AR_PHY_DAG_CTRLCCK);
+       ath_dbg(common, RX_STUCK, "Barker RSSI Thresh Enable = %d\n",
+                       MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR));
+       ath_dbg(common, RX_STUCK, "Barker RSSI Thresh = 0x%x (%d)\n",
+                       MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR),
+                       MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR));
+}
+EXPORT_SYMBOL(ar9003_hw_dump_ani_reg);