mlx4: Implement IP based gids support for RoCE/SRIOV

[cascardo/linux.git] / include / linux / mlx4 / device.h

diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 7d3a523..f211b51 100644 (file)
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -48,6 +48,9 @@
 #define MSIX_LEGACY_SZ         4
 #define MIN_MSIX_P_PORT                5
 
+#define MLX4_ROCE_MAX_GIDS     128
+#define MLX4_ROCE_PF_GIDS      16
+
 enum {
        MLX4_FLAG_MSI_X         = 1 << 0,
        MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
@@ -118,6 +121,11 @@ static inline const char *mlx4_steering_mode_str(int steering_mode)
        }
 }
 
+enum {
+       MLX4_TUNNEL_OFFLOAD_MODE_NONE,
+       MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
+};
+
 enum {
        MLX4_DEV_CAP_FLAG_RC            = 1LL <<  0,
        MLX4_DEV_CAP_FLAG_UC            = 1LL <<  1,
@@ -160,7 +168,9 @@ enum {
        MLX4_DEV_CAP_FLAG2_TS                   = 1LL <<  5,
        MLX4_DEV_CAP_FLAG2_VLAN_CONTROL         = 1LL <<  6,
        MLX4_DEV_CAP_FLAG2_FSM                  = 1LL <<  7,
-       MLX4_DEV_CAP_FLAG2_UPDATE_QP            = 1LL <<  8
+       MLX4_DEV_CAP_FLAG2_UPDATE_QP            = 1LL <<  8,
+       MLX4_DEV_CAP_FLAG2_DMFS_IPOIB           = 1LL <<  9,
+       MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS       = 1LL <<  10,
 };
 
 enum {
@@ -454,6 +464,8 @@ struct mlx4_caps {
        u32                     userspace_caps; /* userspace must be aware of these */
        u32                     function_caps;  /* VFs must be aware of these */
        u16                     hca_core_clock;
+       u64                     phys_port_id[MLX4_MAX_PORTS + 1];
+       int                     tunnel_offload_mode;
 };
 
 struct mlx4_buf_list {
@@ -620,7 +632,8 @@ struct mlx4_eth_av {
        u8              hop_limit;
        __be32          sl_tclass_flowlabel;
        u8              dgid[16];
-       u32             reserved4[2];
+       u8              s_mac[6];
+       u8              reserved4[2];
        __be16          vlan;
        u8              mac[ETH_ALEN];
 };
@@ -908,6 +921,7 @@ enum mlx4_net_trans_rule_id {
        MLX4_NET_TRANS_RULE_ID_IPV4,
        MLX4_NET_TRANS_RULE_ID_TCP,
        MLX4_NET_TRANS_RULE_ID_UDP,
+       MLX4_NET_TRANS_RULE_ID_VXLAN,
        MLX4_NET_TRANS_RULE_NUM, /* should be last */
 };
 
@@ -965,6 +979,12 @@ struct mlx4_spec_ib {
        u8      dst_gid_msk[16];
 };
 
+struct mlx4_spec_vxlan {
+       __be32 vni;
+       __be32 vni_mask;
+
+};
+
 struct mlx4_spec_list {
        struct  list_head list;
        enum    mlx4_net_trans_rule_id id;
@@ -973,6 +993,7 @@ struct mlx4_spec_list {
                struct mlx4_spec_ib ib;
                struct mlx4_spec_ipv4 ipv4;
                struct mlx4_spec_tcp_udp tcp_udp;
+               struct mlx4_spec_vxlan vxlan;
        };
 };
 
@@ -1059,6 +1080,15 @@ struct mlx4_net_trans_rule_hw_ipv4 {
        __be32  src_ip_msk;
 } __packed;
 
+struct mlx4_net_trans_rule_hw_vxlan {
+       u8      size;
+       u8      rsvd;
+       __be16  id;
+       __be32  rsvd1;
+       __be32  vni;
+       __be32  vni_mask;
+} __packed;
+
 struct _rule_hw {
        union {
                struct {
@@ -1070,9 +1100,19 @@ struct _rule_hw {
                struct mlx4_net_trans_rule_hw_ib ib;
                struct mlx4_net_trans_rule_hw_ipv4 ipv4;
                struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
+               struct mlx4_net_trans_rule_hw_vxlan vxlan;
        };
 };
 
+enum {
+       VXLAN_STEER_BY_OUTER_MAC        = 1 << 0,
+       VXLAN_STEER_BY_OUTER_VLAN       = 1 << 1,
+       VXLAN_STEER_BY_VSID_VNI         = 1 << 2,
+       VXLAN_STEER_BY_INNER_MAC        = 1 << 3,
+       VXLAN_STEER_BY_INNER_VLAN       = 1 << 4,
+};
+
+
 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
                                enum mlx4_net_trans_promisc_mode mode);
 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
@@ -1095,6 +1135,8 @@ int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
                u8 *pg, u16 *ratelimit);
+int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering);
+int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
@@ -1113,6 +1155,7 @@ int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
                   int *vector);
 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
 
+int mlx4_get_phys_port_id(struct mlx4_dev *dev);
 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
 
@@ -1144,6 +1187,14 @@ int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int
 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
 
+int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
+                                int *slave_id);
+int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
+                                u8 *gid);
+
+int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
+                                     u32 max_range_qpn);
+
 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
 
 #endif /* MLX4_DEVICE_H */