net/mlx5_core: HW data structs/types definitions cleanup

[cascardo/linux.git] / include / linux / mlx5 / device.h

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index abf65c7..feebed7 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -35,6 +35,7 @@
 
 #include <linux/types.h>
 #include <rdma/ib_verbs.h>
+#include <linux/mlx5/mlx5_ifc.h>
 
 #if defined(__LITTLE_ENDIAN)
 #define MLX5_SET_HOST_ENDIANNESS       0
@@ -70,6 +71,14 @@
                     << __mlx5_dw_bit_off(typ, fld))); \
 } while (0)
 
+#define MLX5_SET_TO_ONES(typ, p, fld) do { \
+       BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
+       *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
+       cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
+                    (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
+                    << __mlx5_dw_bit_off(typ, fld))); \
+} while (0)
+
 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 __mlx5_mask(typ, fld))
@@ -264,6 +273,7 @@ enum {
        MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
        MLX5_OPCODE_SEND                = 0x0a,
        MLX5_OPCODE_SEND_IMM            = 0x0b,
+       MLX5_OPCODE_LSO                 = 0x0e,
        MLX5_OPCODE_RDMA_READ           = 0x10,
        MLX5_OPCODE_ATOMIC_CS           = 0x11,
        MLX5_OPCODE_ATOMIC_FA           = 0x12,
@@ -541,6 +551,10 @@ struct mlx5_cmd_prot_block {
        u8              sig;
 };
 
+enum {
+       MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
+};
+
 struct mlx5_err_cqe {
        u8      rsvd0[32];
        __be32  srqn;
@@ -554,13 +568,22 @@ struct mlx5_err_cqe {
 };
 
 struct mlx5_cqe64 {
-       u8              rsvd0[17];
+       u8              rsvd0[4];
+       u8              lro_tcppsh_abort_dupack;
+       u8              lro_min_ttl;
+       __be16          lro_tcp_win;
+       __be32          lro_ack_seq_num;
+       __be32          rss_hash_result;
+       u8              rss_hash_type;
        u8              ml_path;
-       u8              rsvd20[4];
+       u8              rsvd20[2];
+       __be16          check_sum;
        __be16          slid;
        __be32          flags_rqpn;
-       u8              rsvd28[4];
-       __be32          srqn;
+       u8              hds_ip_ext;
+       u8              l4_hdr_type_etc;
+       __be16          vlan_info;
+       __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
        __be32          imm_inval_pkey;
        u8              rsvd40[4];
        __be32          byte_cnt;
@@ -571,6 +594,40 @@ struct mlx5_cqe64 {
        u8              op_own;
 };
 
+static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
+{
+       return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
+}
+
+static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
+{
+       return (cqe->l4_hdr_type_etc >> 4) & 0x7;
+}
+
+static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
+{
+       return !!(cqe->l4_hdr_type_etc & 0x1);
+}
+
+enum {
+       CQE_L4_HDR_TYPE_NONE                    = 0x0,
+       CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
+       CQE_L4_HDR_TYPE_UDP                     = 0x2,
+       CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
+       CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
+};
+
+enum {
+       CQE_RSS_HTYPE_IP        = 0x3 << 6,
+       CQE_RSS_HTYPE_L4        = 0x3 << 2,
+};
+
+enum {
+       CQE_L2_OK       = 1 << 0,
+       CQE_L3_OK       = 1 << 1,
+       CQE_L4_OK       = 1 << 2,
+};
+
 struct mlx5_sig_err_cqe {
        u8              rsvd0[16];
        __be32          expected_trans_sig;
@@ -996,4 +1053,52 @@ struct mlx5_destroy_psv_out {
        u8                      rsvd[8];
 };
 
+#define MLX5_CMD_OP_MAX 0x920
+
+enum {
+       VPORT_STATE_DOWN                = 0x0,
+       VPORT_STATE_UP                  = 0x1,
+};
+
+enum {
+       MLX5_L3_PROT_TYPE_IPV4          = 0,
+       MLX5_L3_PROT_TYPE_IPV6          = 1,
+};
+
+enum {
+       MLX5_L4_PROT_TYPE_TCP           = 0,
+       MLX5_L4_PROT_TYPE_UDP           = 1,
+};
+
+enum {
+       MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
+       MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
+       MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
+       MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
+       MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
+};
+
+enum {
+       MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
+       MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
+       MLX5_MATCH_INNER_HEADERS        = 1 << 2,
+
+};
+
+enum {
+       MLX5_FLOW_TABLE_TYPE_NIC_RCV    = 0,
+       MLX5_FLOW_TABLE_TYPE_ESWITCH    = 4,
+};
+
+enum {
+       MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT       = 0,
+       MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE  = 1,
+       MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
+};
+
+enum {
+       MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
+       MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
+};
+
 #endif /* MLX5_DEVICE_H */