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net/mlx5: E-Switch, Add SR-IOV (FDB) support
[cascardo/linux.git] / include / linux / mlx5 / mlx5_ifc.h
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index dd20974..a81b008 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -447,32 +447,46 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
        u8         reserved_3[0x7200];
 };
 
+struct mlx5_ifc_flow_table_eswitch_cap_bits {
+       u8     reserved_0[0x200];
+
+       struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
+
+       struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
+
+       struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
+
+       u8      reserved_1[0x7800];
+};
+
 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
        u8         csum_cap[0x1];
        u8         vlan_cap[0x1];
        u8         lro_cap[0x1];
        u8         lro_psh_flag[0x1];
        u8         lro_time_stamp[0x1];
-       u8         reserved_0[0x6];
+       u8         reserved_0[0x3];
+       u8         self_lb_en_modifiable[0x1];
+       u8         reserved_1[0x2];
        u8         max_lso_cap[0x5];
-       u8         reserved_1[0x4];
+       u8         reserved_2[0x4];
        u8         rss_ind_tbl_cap[0x4];
-       u8         reserved_2[0x3];
+       u8         reserved_3[0x3];
        u8         tunnel_lso_const_out_ip_id[0x1];
-       u8         reserved_3[0x2];
+       u8         reserved_4[0x2];
        u8         tunnel_statless_gre[0x1];
        u8         tunnel_stateless_vxlan[0x1];
 
-       u8         reserved_4[0x20];
+       u8         reserved_5[0x20];
 
-       u8         reserved_5[0x10];
+       u8         reserved_6[0x10];
        u8         lro_min_mss_size[0x10];
 
-       u8         reserved_6[0x120];
+       u8         reserved_7[0x120];
 
        u8         lro_timer_supported_periods[4][0x20];
 
-       u8         reserved_7[0x600];
+       u8         reserved_8[0x600];
 };
 
 struct mlx5_ifc_roce_cap_bits {
@@ -663,7 +677,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_17[0x1];
        u8         ets[0x1];
        u8         nic_flow_table[0x1];
-       u8         reserved_18[0x4];
+       u8         eswitch_flow_table[0x1];
+       u8         early_vf_enable;
+       u8         reserved_18[0x2];
        u8         local_ca_ack_delay[0x5];
        u8         reserved_19[0x6];
        u8         port_type[0x2];
@@ -785,27 +801,36 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_60[0x1b];
        u8         log_max_wq_sz[0x5];
 
-       u8         reserved_61[0xa0];
-
+       u8         nic_vport_change_event[0x1];
+       u8         reserved_61[0xa];
+       u8         log_max_vlan_list[0x5];
        u8         reserved_62[0x3];
+       u8         log_max_current_mc_list[0x5];
+       u8         reserved_63[0x3];
+       u8         log_max_current_uc_list[0x5];
+
+       u8         reserved_64[0x80];
+
+       u8         reserved_65[0x3];
        u8         log_max_l2_table[0x5];
-       u8         reserved_63[0x8];
+       u8         reserved_66[0x8];
        u8         log_uar_page_sz[0x10];
 
-       u8         reserved_64[0x100];
+       u8         reserved_67[0xe0];
 
-       u8         reserved_65[0x1f];
+       u8         reserved_68[0x1f];
        u8         cqe_zip[0x1];
 
        u8         cqe_zip_timeout[0x10];
        u8         cqe_zip_max_num[0x10];
 
-       u8         reserved_66[0x220];
+       u8         reserved_69[0x220];
 };
 
-enum {
-       MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_  = 0x1,
-       MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR          = 0x2,
+enum mlx5_flow_destination_type {
+       MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
+       MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
+       MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 };
 
 struct mlx5_ifc_dest_format_struct_bits {
@@ -898,6 +923,13 @@ struct mlx5_ifc_mac_address_layout_bits {
        u8         mac_addr_31_0[0x20];
 };
 
+struct mlx5_ifc_vlan_layout_bits {
+       u8         reserved_0[0x14];
+       u8         vlan[0x0c];
+
+       u8         reserved_1[0x20];
+};
+
 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
        u8         reserved_0[0xa0];
 
@@ -1827,6 +1859,7 @@ union mlx5_ifc_hca_cap_union_bits {
        struct mlx5_ifc_roce_cap_bits roce_cap;
        struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
        struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
+       struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
        u8         reserved_0[0x8000];
 };
 
@@ -2131,24 +2164,35 @@ struct mlx5_ifc_rmpc_bits {
        struct mlx5_ifc_wq_bits wq;
 };
 
-enum {
-       MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
-};
-
 struct mlx5_ifc_nic_vport_context_bits {
        u8         reserved_0[0x1f];
        u8         roce_en[0x1];
 
-       u8         reserved_1[0x760];
+       u8         arm_change_event[0x1];
+       u8         reserved_1[0x1a];
+       u8         event_on_mtu[0x1];
+       u8         event_on_promisc_change[0x1];
+       u8         event_on_vlan_change[0x1];
+       u8         event_on_mc_address_change[0x1];
+       u8         event_on_uc_address_change[0x1];
 
-       u8         reserved_2[0x5];
+       u8         reserved_2[0xf0];
+
+       u8         mtu[0x10];
+
+       u8         reserved_3[0x640];
+
+       u8         promisc_uc[0x1];
+       u8         promisc_mc[0x1];
+       u8         promisc_all[0x1];
+       u8         reserved_4[0x2];
        u8         allowed_list_type[0x3];
-       u8         reserved_3[0xc];
+       u8         reserved_5[0xc];
        u8         allowed_list_size[0xc];
 
        struct mlx5_ifc_mac_address_layout_bits permanent_address;
 
-       u8         reserved_4[0x20];
+       u8         reserved_6[0x20];
 
        u8         current_uc_mac_address[0][0x40];
 };
@@ -2938,6 +2982,7 @@ struct mlx5_ifc_query_vport_state_out_bits {
 
 enum {
        MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
+       MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
 };
 
 struct mlx5_ifc_query_vport_state_in_bits {
@@ -4051,9 +4096,11 @@ struct mlx5_ifc_modify_tis_in_bits {
 };
 
 struct mlx5_ifc_modify_tir_bitmask_bits {
-       u8         reserved[0x20];
+       u8         reserved_0[0x20];
 
-       u8         reserved1[0x1f];
+       u8         reserved_1[0x1b];
+       u8         self_lb_en[0x1];
+       u8         reserved_2[0x3];
        u8         lro[0x1];
 };
 
@@ -4224,7 +4271,10 @@ struct mlx5_ifc_modify_nic_vport_context_out_bits {
 };
 
 struct mlx5_ifc_modify_nic_vport_field_select_bits {
-       u8         reserved_0[0x1c];
+       u8         reserved_0[0x19];
+       u8         mtu[0x1];
+       u8         change_event[0x1];
+       u8         promisc[0x1];
        u8         permanent_address[0x1];
        u8         addresses_list[0x1];
        u8         roce_en[0x1];
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