unsigned int irq;
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
+ bool match_driver; /* Skip attaching driver */
/* These fields are used by common fixups */
unsigned int transparent:1; /* Transparent PCI bridge */
unsigned int multifunction:1;/* Part of multi-function device */
void (*release_fn)(struct pci_host_bridge *),
void *release_data);
+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
+
/*
* The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
* to P2P or CardBus bridge windows) go in a table. Additional ones (for
/* Some device drivers need know if pci is initiated */
extern int no_pci_devices(void);
+void pcibios_resource_survey_bus(struct pci_bus *bus);
void pcibios_fixup_bus(struct pci_bus *);
int __must_check pcibios_enable_device(struct pci_dev *, int mask);
/* Architecture specific versions may override this (weak) */
return !!pci_pcie_cap(dev);
}
+/**
+ * pcie_caps_reg - get the PCIe Capabilities Register
+ * @dev: PCI device
+ */
+static inline u16 pcie_caps_reg(const struct pci_dev *dev)
+{
+ return dev->pcie_flags_reg;
+}
+
/**
* pci_pcie_type - get the PCIe device/port type
* @dev: PCI device
*/
static inline int pci_pcie_type(const struct pci_dev *dev)
{
- return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
+ return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
}
void pci_request_acs(void);