X-Git-Url: http://git.cascardo.eti.br/?a=blobdiff_plain;f=Documentation%2Fparisc%2Fregisters;fp=Documentation%2Fparisc%2Fregisters;h=10c7d1730f5d8ccd0e7ace717627a2b1efe837b4;hb=a83f58bcb24003b9de2364de7c829a263423ead7;hp=dd3caddd1ad9859914defe892c359e864690acac;hpb=30a9f0b251285ba29f09a7134eee07a4c3aca639;p=cascardo%2Flinux.git

diff --git a/Documentation/parisc/registers b/Documentation/parisc/registers
index dd3caddd1ad9..10c7d1730f5d 100644
--- a/Documentation/parisc/registers
+++ b/Documentation/parisc/registers
@@ -77,6 +77,14 @@ PSW default E value		0
 Shadow Registers		used by interruption handler code
 TOC enable bit			1
 
+=========================================================================
+
+The PA-RISC architecture defines 7 registers as "shadow registers".
+Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce
+the state save and restore time by eliminating the need for general register
+(GR) saves and restores in interruption handlers.
+Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25.
+
 =========================================================================
 Register usage notes, originally from John Marvin, with some additional
 notes from Randolph Chung.