X-Git-Url: http://git.cascardo.eti.br/?a=blobdiff_plain;f=arch%2Favr32%2Fboards%2Ffavr-32%2Fsetup.c;h=1a12930df8e7956451939e49df5efe57f0adf0d0;hb=0e490050902adaca9b30275ec9a544a786bf2db8;hp=7538f3d2b9e0742a4a5647cc37a5b1fa7f6e611d;hpb=4ac08d36aa9c556556c7b150caee263c6d542645;p=cascardo%2Flinux.git diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c index 7538f3d2b9e0..1a12930df8e7 100644 --- a/arch/avr32/boards/favr-32/setup.c +++ b/arch/avr32/boards/favr-32/setup.c @@ -25,10 +25,10 @@ #include -#include -#include -#include -#include +#include +#include +#include +#include /* Oscillator frequencies. These are board-specific */ unsigned long at32_board_osc_rates[3] = { @@ -307,28 +307,10 @@ static int __init favr32_init(void) * Favr-32 uses 32-bit SDRAM interface. Reserve the SDRAM-specific * pins so that nobody messes with them. */ - at32_reserve_pin(GPIO_PIN_PE(0)); /* DATA[16] */ - at32_reserve_pin(GPIO_PIN_PE(1)); /* DATA[17] */ - at32_reserve_pin(GPIO_PIN_PE(2)); /* DATA[18] */ - at32_reserve_pin(GPIO_PIN_PE(3)); /* DATA[19] */ - at32_reserve_pin(GPIO_PIN_PE(4)); /* DATA[20] */ - at32_reserve_pin(GPIO_PIN_PE(5)); /* DATA[21] */ - at32_reserve_pin(GPIO_PIN_PE(6)); /* DATA[22] */ - at32_reserve_pin(GPIO_PIN_PE(7)); /* DATA[23] */ - at32_reserve_pin(GPIO_PIN_PE(8)); /* DATA[24] */ - at32_reserve_pin(GPIO_PIN_PE(9)); /* DATA[25] */ - at32_reserve_pin(GPIO_PIN_PE(10)); /* DATA[26] */ - at32_reserve_pin(GPIO_PIN_PE(11)); /* DATA[27] */ - at32_reserve_pin(GPIO_PIN_PE(12)); /* DATA[28] */ - at32_reserve_pin(GPIO_PIN_PE(13)); /* DATA[29] */ - at32_reserve_pin(GPIO_PIN_PE(14)); /* DATA[30] */ - at32_reserve_pin(GPIO_PIN_PE(15)); /* DATA[31] */ - at32_reserve_pin(GPIO_PIN_PE(26)); /* SDCS */ + at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL); at32_select_gpio(GPIO_PIN_PB(3), 0); /* IRQ from ADS7843 */ - at32_add_system_devices(); - at32_add_device_usart(0); set_hw_addr(at32_add_device_eth(0, ð_data[0]));