X-Git-Url: http://git.cascardo.eti.br/?a=blobdiff_plain;f=drivers%2Fedac%2Fi82860_edac.c;h=bd7bbb733f79f3d64aa261eb1765b2a9c9972f20;hb=b4e8b37201d647e4b4abb89d57ebdb8c739d5405;hp=942129df0212465559b4e87ed9c01a42df8fc3fd;hpb=749ede57443b2a7ede2db105145f21047efcea6a;p=cascardo%2Flinux.git diff --git a/drivers/edac/i82860_edac.c b/drivers/edac/i82860_edac.c index 942129df0212..bd7bbb733f79 100644 --- a/drivers/edac/i82860_edac.c +++ b/drivers/edac/i82860_edac.c @@ -9,23 +9,21 @@ * by Thayne Harbaugh of Linux Networx. (http://lnxi.com) */ - -#include #include #include #include #include #include -#include "edac_mc.h" +#include "edac_core.h" +#define I82860_REVISION " Ver: 2.0.2 " __DATE__ +#define EDAC_MOD_STR "i82860_edac" #define i82860_printk(level, fmt, arg...) \ - edac_printk(level, "i82860", fmt, ##arg) - + edac_printk(level, "i82860", fmt, ##arg) #define i82860_mc_printk(mci, level, fmt, arg...) \ - edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg) - + edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg) #ifndef PCI_DEVICE_ID_INTEL_82860_0 #define PCI_DEVICE_ID_INTEL_82860_0 0x2531 @@ -60,22 +58,27 @@ static const struct i82860_dev_info i82860_devs[] = { }; static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code - has already registered driver */ + * has already registered driver + */ -static void i82860_get_error_info (struct mem_ctl_info *mci, - struct i82860_error_info *info) +static void i82860_get_error_info(struct mem_ctl_info *mci, + struct i82860_error_info *info) { + struct pci_dev *pdev; + + pdev = to_pci_dev(mci->dev); + /* * This is a mess because there is no atomic way to read all the * registers at once and the registers can transition from CE being * overwritten by UE. */ - pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts); - pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap); - pci_read_config_word(mci->pdev, I82860_DERRCTL_STS, &info->derrsyn); - pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts2); + pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts); + pci_read_config_dword(pdev, I82860_EAP, &info->eap); + pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn); + pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2); - pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003); + pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003); /* * If the error is the same for both reads then the first set of reads @@ -84,15 +87,16 @@ static void i82860_get_error_info (struct mem_ctl_info *mci, */ if (!(info->errsts2 & 0x0003)) return; + if ((info->errsts ^ info->errsts2) & 0x0003) { - pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap); - pci_read_config_word(mci->pdev, I82860_DERRCTL_STS, - &info->derrsyn); + pci_read_config_dword(pdev, I82860_EAP, &info->eap); + pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn); } } -static int i82860_process_error_info (struct mem_ctl_info *mci, - struct i82860_error_info *info, int handle_errors) +static int i82860_process_error_info(struct mem_ctl_info *mci, + struct i82860_error_info *info, + int handle_errors) { int row; @@ -113,8 +117,8 @@ static int i82860_process_error_info (struct mem_ctl_info *mci, if (info->errsts & 0x0002) edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE"); else - edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, - 0, "i82860 UE"); + edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0, + "i82860 UE"); return 1; } @@ -128,15 +132,50 @@ static void i82860_check(struct mem_ctl_info *mci) i82860_process_error_info(mci, &info, 1); } -static int i82860_probe1(struct pci_dev *pdev, int dev_idx) +static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev) { - int rc = -ENODEV; - int index; - struct mem_ctl_info *mci = NULL; unsigned long last_cumul_size; - struct i82860_error_info discard; + u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ + u16 value; + u32 cumul_size; + struct csrow_info *csrow; + int index; + + pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim); + mchcfg_ddim = mchcfg_ddim & 0x180; + last_cumul_size = 0; - u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ + /* The group row boundary (GRA) reg values are boundary address + * for each DRAM row with a granularity of 16MB. GRA regs are + * cumulative; therefore GRA15 will contain the total memory contained + * in all eight rows. + */ + for (index = 0; index < mci->nr_csrows; index++) { + csrow = &mci->csrows[index]; + pci_read_config_word(pdev, I82860_GBA + index * 2, &value); + cumul_size = (value & I82860_GBA_MASK) << + (I82860_GBA_SHIFT - PAGE_SHIFT); + debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, + cumul_size); + + if (cumul_size == last_cumul_size) + continue; /* not populated */ + + csrow->first_page = last_cumul_size; + csrow->last_page = cumul_size - 1; + csrow->nr_pages = cumul_size - last_cumul_size; + last_cumul_size = cumul_size; + csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */ + csrow->mtype = MEM_RMBS; + csrow->dtype = DEV_UNKNOWN; + csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE; + } +} + +static int i82860_probe1(struct pci_dev *pdev, int dev_idx) +{ + struct mem_ctl_info *mci; + struct i82860_error_info discard; /* RDRAM has channels but these don't map onto the abstractions that edac uses. @@ -147,71 +186,41 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx) going to make 1 channel for group. */ mci = edac_mc_alloc(0, 16, 1); + if (!mci) return -ENOMEM; debugf3("%s(): init mci\n", __func__); - - mci->pdev = pdev; + mci->dev = &pdev->dev; mci->mtype_cap = MEM_FLAG_DDR; - - mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; /* I"m not sure about this but I think that all RDRAM is SECDED */ mci->edac_cap = EDAC_FLAG_SECDED; - /* adjust FLAGS */ - mci->mod_name = EDAC_MOD_STR; - mci->mod_ver = "$Revision: 1.1.2.6 $"; + mci->mod_ver = I82860_REVISION; mci->ctl_name = i82860_devs[dev_idx].ctl_name; + mci->dev_name = pci_name(pdev); mci->edac_check = i82860_check; mci->ctl_page_to_phys = NULL; + i82860_init_csrows(mci, pdev); + i82860_get_error_info(mci, &discard); /* clear counters */ - pci_read_config_word(mci->pdev, I82860_MCHCFG, &mchcfg_ddim); - mchcfg_ddim = mchcfg_ddim & 0x180; - - /* - * The group row boundary (GRA) reg values are boundary address - * for each DRAM row with a granularity of 16MB. GRA regs are - * cumulative; therefore GRA15 will contain the total memory contained - * in all eight rows. + /* Here we assume that we will never see multiple instances of this + * type of memory controller. The ID is therefore hardcoded to 0. */ - for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { - u16 value; - u32 cumul_size; - struct csrow_info *csrow = &mci->csrows[index]; - - pci_read_config_word(mci->pdev, I82860_GBA + index * 2, - &value); - - cumul_size = (value & I82860_GBA_MASK) << - (I82860_GBA_SHIFT - PAGE_SHIFT); - debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, - cumul_size); - if (cumul_size == last_cumul_size) - continue; /* not populated */ - - csrow->first_page = last_cumul_size; - csrow->last_page = cumul_size - 1; - csrow->nr_pages = cumul_size - last_cumul_size; - last_cumul_size = cumul_size; - csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */ - csrow->mtype = MEM_RMBS; - csrow->dtype = DEV_UNKNOWN; - csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE; + if (edac_mc_add_mc(mci, 0)) { + debugf3("%s(): failed edac_mc_add_mc()\n", __func__); + goto fail; } - i82860_get_error_info(mci, &discard); /* clear counters */ + /* get this far and it's successful */ + debugf3("%s(): success\n", __func__); - if (edac_mc_add_mc(mci)) { - debugf3("%s(): failed edac_mc_add_mc()\n", __func__); - edac_mc_free(mci); - } else { - /* get this far and it's successful */ - debugf3("%s(): success\n", __func__); - rc = 0; - } - return rc; + return 0; + + fail: + edac_mc_free(mci); + return -ENODEV; } /* returns count (>= 0), or negative on error */ @@ -221,13 +230,16 @@ static int __devinit i82860_init_one(struct pci_dev *pdev, int rc; debugf0("%s()\n", __func__); - i82860_printk(KERN_INFO, "i82860 init one\n"); - if(pci_enable_device(pdev) < 0) + + if (pci_enable_device(pdev) < 0) return -EIO; + rc = i82860_probe1(pdev, ent->driver_data); - if(rc == 0) + + if (rc == 0) mci_pdev = pci_dev_get(pdev); + return rc; } @@ -237,15 +249,19 @@ static void __devexit i82860_remove_one(struct pci_dev *pdev) debugf0("%s()\n", __func__); - mci = edac_mc_find_mci_by_pdev(pdev); - if ((mci != NULL) && (edac_mc_del_mc(mci) == 0)) - edac_mc_free(mci); + if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) + return; + + edac_mc_free(mci); } static const struct pci_device_id i82860_pci_tbl[] __devinitdata = { - {PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, + { + PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, I82860}, - {0,} /* 0 terminated list. */ + { + 0, + } /* 0 terminated list. */ }; MODULE_DEVICE_TABLE(pci, i82860_pci_tbl); @@ -262,30 +278,35 @@ static int __init i82860_init(void) int pci_rc; debugf3("%s()\n", __func__); + if ((pci_rc = pci_register_driver(&i82860_driver)) < 0) goto fail0; if (!mci_pdev) { mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82860_0, NULL); + if (mci_pdev == NULL) { debugf0("860 pci_get_device fail\n"); pci_rc = -ENODEV; goto fail1; } + pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl); + if (pci_rc < 0) { debugf0("860 init fail\n"); pci_rc = -ENODEV; goto fail1; } } + return 0; -fail1: + fail1: pci_unregister_driver(&i82860_driver); -fail0: + fail0: if (mci_pdev != NULL) pci_dev_put(mci_pdev); @@ -306,6 +327,6 @@ module_init(i82860_init); module_exit(i82860_exit); MODULE_LICENSE("GPL"); -MODULE_AUTHOR - ("Red Hat Inc. (http://www.redhat.com) Ben Woodard "); +MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) " + "Ben Woodard "); MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");