KVM: PPC: Book3S PR: Handle PP0 page-protection bit in guest HPTEs
authorPaul Mackerras <paulus@samba.org>
Fri, 20 Sep 2013 04:52:46 +0000 (14:52 +1000)
committerAlexander Graf <agraf@suse.de>
Thu, 17 Oct 2013 12:45:04 +0000 (14:45 +0200)
commit03a9c90334d611c3006ac9569579f25f64812bc1
tree8bac356754c5a13b47a15f8a7d7b8726a42b5d38
parentc9029c341da646ab0c9911ea4c118eaa0a2eb0fa
KVM: PPC: Book3S PR: Handle PP0 page-protection bit in guest HPTEs

64-bit POWER processors have a three-bit field for page protection in
the hashed page table entry (HPTE).  Currently we only interpret the two
bits that were present in older versions of the architecture.  The only
defined combination that has the new bit set is 110, meaning read-only
for supervisor and no access for user mode.

This adds code to kvmppc_mmu_book3s_64_xlate() to interpret the extra
bit appropriately.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
arch/powerpc/kvm/book3s_64_mmu.c