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clk: samsung: exynos5433: Add clocks for CMU_MIF domain
authorChanwoo Choi <cw00.choi@samsung.com>
Mon, 2 Feb 2015 14:24:01 +0000 (23:24 +0900)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Wed, 4 Feb 2015 17:58:11 +0000 (18:58 +0100)
commit06d2f9dfa663367e8cc1690d7e5ce4113e5dbcc1
treec691b7076f3a94d18ddc7279e8a0416c2f9e4a90tree | snapshot
parenta29308dad5dc4695a344ed9042cae8a1b8e35267commit | diff
clk: samsung: exynos5433: Add clocks for CMU_MIF domain

This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5433.c diff | blob | history
include/dt-bindings/clock/exynos5433.h diff | blob | history
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