git.cascardo.eti.br Git - cascardo/linux.git/commit

author	Ville Syrjälä <ville.syrjala@linux.intel.com>
	Wed, 9 Apr 2014 10:28:37 +0000 (13:28 +0300)
committer	Daniel Vetter <daniel.vetter@ffwll.ch>
	Tue, 20 May 2014 13:19:39 +0000 (15:19 +0200)
commit	0846697c6710a83bdacfe92b92c03288d87e24d9
tree	1d6ec8aff0ec98aacca757f35d66b5658efe9213	tree \| snapshot
parent	acea6f9573904a9591244123afc769139bbd3fc6	commit \| diff

drm/i915/chv: Implement WaDisableCSUnitClockGating:chv

This workaround is listed for CHV, but not for BDW. However BSpec notes
that on BDW CSunit clock gating is always disabled irrespective of the
relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text
is not present in BSpec, so it seems safer to just set the bit.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>