drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Fri, 10 Apr 2015 18:15:08 +0000 (11:15 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 14 Apr 2015 17:15:01 +0000 (19:15 +0200)
commit3301d4092106ff07e14d7acbf12243d782600930
tree61e839f3cb7cdfa39878e9c43bbdc72dbfa53bec
parentcff5190cb989f130afa18b96cd33745b733ffae9
drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

Since the beginning there is a missunderstanding on the meaning of this
dpcd bit.
This bit shouldn't indicate whether to use link standby or not, but just
be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
since HW is the responsible one.

Even with help of frontbuffer tracking, HW is still fully responsible for
PSR exit logic with/without DP training.

DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the training, but
it doesn't tell to avoid TP patterns, so we will send minimal TP1 and avoid
TP2. It also means that sink itself can take up to 5 idle frames for training.
6 in our case since we might be off by 1. So we also increment idle_frames by 4
here.

v2: Fix and improve commit message (Durga).
v3: Use minimal TP1 time avoiding TP2 and increase idle frame.

Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_psr.c