clk: iproc: Fix PLL output frequency calculation
authorSimran Rai <ssimran@broadcom.com>
Mon, 19 Oct 2015 22:27:19 +0000 (15:27 -0700)
committerMichael Turquette <mturquette@baylibre.com>
Wed, 21 Oct 2015 09:43:57 +0000 (02:43 -0700)
commit63243a4da7d0dfa19dcacd0a529782eeb2f86f92
tree98b30265294172b55b6f7f195d5d56e5ad9535f6
parent1256f10fb26e5824fde12314b5f4690797478678
clk: iproc: Fix PLL output frequency calculation

This patch affects the clocks that use fractional ndivider in their
PLL output frequency calculation. Instead of 2^20 divide factor, the
clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
integer shift with 2^20 factor.

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
Cc: <stable@vger.kernel.org> # v4.1+
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drivers/clk/bcm/clk-iproc-pll.c