x86, cpu: Detect more TLB configuration
authorKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Mon, 23 Dec 2013 12:16:58 +0000 (14:16 +0200)
committerH. Peter Anvin <hpa@linux.intel.com>
Fri, 3 Jan 2014 22:35:42 +0000 (14:35 -0800)
commitdd360393f4d948eb518372316e52101cf3b44212
tree7b664120f6ea4de3adb75acc9d05fbf15356f1cc
parent802eee95bde72fd0cd0f3a5b2098375a487d1eda
x86, cpu: Detect more TLB configuration

The Intel Software Developer’s Manual covers few more TLB
configurations exposed as CPUID 2 descriptors:

61H Instruction TLB: 4 KByte pages, fully associative, 48 entries
63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries
76H Instruction TLB: 2M/4M pages, fully associative, 8 entries
B5H Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
B6H Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
C1H Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
C2H DTLB DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries

Let's detect them as well.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: http://lkml.kernel.org/r/1387801018-14499-1-git-send-email-kirill.shutemov@linux.intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
arch/x86/include/asm/processor.h
arch/x86/kernel/cpu/common.c
arch/x86/kernel/cpu/intel.c