ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Wed, 19 Aug 2015 05:49:26 +0000 (14:49 +0900)
committerOlof Johansson <olof@lixom.net>
Fri, 21 Aug 2015 01:28:39 +0000 (18:28 -0700)
commitf2032f24c0e51487d88c3555db12e27d561e4f14
treed7b2cf20932073c6c7589a4d2b94dddffaaf2166
parent62060a3548c5ea038b4ade518cce92be32a6718d
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes

This SoC is integrated with 4 Cortex-A9 cores.  The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask.  Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm/boot/dts/uniphier-proxstream2.dtsi