This commit adds pin-mux nodes for the NAND controller.
Some SoCs support 2 chip selects and the others only support
1 chip select.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+ pinctrl_nand: nand_grp {
+ groups = "nand";
+ function = "nand";
+ };
+
+ pinctrl_nand2cs: nand2cs_grp {
+ groups = "nand", "nand_cs1";
+ function = "nand";
+ };
+
pinctrl_uart0: uart0_grp {
groups = "uart0";
function = "uart0";
pinctrl_uart0: uart0_grp {
groups = "uart0";
function = "uart0";