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ea0e0a4)
"extern inline" doesn't make much sense.
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
*/
#define div_long_long_rem(a,b,c) div_ll_X_l_rem(a,b,c)
*/
#define div_long_long_rem(a,b,c) div_ll_X_l_rem(a,b,c)
div_ll_X_l_rem(long long divs, long div, long *rem)
{
long dum2;
div_ll_X_l_rem(long long divs, long div, long *rem)
{
long dum2;
However we don't do prefetches for pre XP Athlons currently
That should be fixed. */
#define ARCH_HAS_PREFETCH
However we don't do prefetches for pre XP Athlons currently
That should be fixed. */
#define ARCH_HAS_PREFETCH
-extern inline void prefetch(const void *x)
+static inline void prefetch(const void *x)
{
alternative_input(ASM_NOP4,
"prefetchnta (%1)",
{
alternative_input(ASM_NOP4,
"prefetchnta (%1)",
/* 3dnow! prefetch to get an exclusive cache line. Useful for
spinlocks to avoid one state transition in the cache coherency protocol. */
/* 3dnow! prefetch to get an exclusive cache line. Useful for
spinlocks to avoid one state transition in the cache coherency protocol. */
-extern inline void prefetchw(const void *x)
+static inline void prefetchw(const void *x)
{
alternative_input(ASM_NOP4,
"prefetchw (%1)",
{
alternative_input(ASM_NOP4,
"prefetchw (%1)",