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b97d0b9)
This code makes large use of barriers, which had quite vague
descriptions. Update the comments to make the choice of barrier and
reason for it more clear.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14220/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
i * line_size * line_stride, t0);
}
i * line_size * line_stride, t0);
}
- /* Completion barrier */
+ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(pp, stype_memory);
uasm_i_ehb(pp);
uasm_i_sync(pp, stype_memory);
uasm_i_ehb(pp);
uasm_il_beqz(&p, &r, t2, lbl_incready);
uasm_i_addiu(&p, t1, t1, 1);
uasm_il_beqz(&p, &r, t2, lbl_incready);
uasm_i_addiu(&p, t1, t1, 1);
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
/*
uasm_i_sync(&p, stype_ordering);
/*
cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
Index_Writeback_Inv_D, lbl_flushdcache);
cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
Index_Writeback_Inv_D, lbl_flushdcache);
- /* Completion barrier */
+ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
- /* Sync to ensure previous interventions are complete */
+ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_intervention);
uasm_i_ehb(&p);
uasm_i_sync(&p, stype_intervention);
uasm_i_ehb(&p);
- /* Completion barrier */
+ /* Barrier to ensure write to CPC command is complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
}
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
}
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
- /* Completion barrier */
+ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
uasm_il_beqz(&p, &r, t2, lbl_decready);
uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
uasm_il_beqz(&p, &r, t2, lbl_decready);
uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
}
uasm_i_sync(&p, stype_ordering);
}
*/
uasm_build_label(&l, p, lbl_secondary_cont);
*/
uasm_build_label(&l, p, lbl_secondary_cont);
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
}
uasm_i_sync(&p, stype_ordering);
}