drm/amd/powerplay: fix typo error when set clock gate state.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
index e1b649b..5afe820 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
@@ -56,7 +56,7 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                fiji_update_uvd_dpm(hwmgr, false);
                cgs_set_clockgating_state(hwmgr->device,
                                          AMD_IP_BLOCK_TYPE_UVD,
-                                         AMD_PG_STATE_UNGATE);
+                                         AMD_CG_STATE_UNGATE);
        }
 
        return 0;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
index aeec25c..423ab63 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
@@ -116,7 +116,7 @@ int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                polaris10_update_uvd_dpm(hwmgr, false);
                cgs_set_clockgating_state(hwmgr->device,
                                AMD_IP_BLOCK_TYPE_UVD,
-                               AMD_PG_STATE_UNGATE);
+                               AMD_CG_STATE_UNGATE);
        }
 
        return 0;