ARM: Exynos: Set 70.25Mhz for pixel clock and adjust snow LCD timings
authorAjay Kumar <ajaykumar.rs@samsung.com>
Thu, 2 Aug 2012 07:27:28 +0000 (03:27 -0400)
committerGerrit <chrome-bot@google.com>
Fri, 3 Aug 2012 23:24:40 +0000 (16:24 -0700)
This patch sets sclk_fimd to 70.25Mhz and
LCD timings are adjusted to get a refresh rate~=60
in both the cases(only LCD and LCD + HDMI).

BUG=chrome-os-partner:11695
TEST=LCD, HDMI and Gscaler are working fine on snow.

Change-Id: Ie301fcb2e4f3e16610a24cac756c2b63cf4e2fa7
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/28938
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Commit-Ready: Doug Anderson <dianders@chromium.org>

arch/arm/mach-exynos/mach-exynos5-dt.c

index 707abf2..5fb0987 100644 (file)
@@ -139,22 +139,22 @@ static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 
 static struct fb_videomode snow_fb_window[] = {
        [0] = { /* Only LCD Connected */
-               .left_margin    = 0,
-               .right_margin   = 0,
-               .upper_margin   = 4,
-               .lower_margin   = 4,
-               .hsync_len      = 5,
-               .vsync_len      = 32,
+               .left_margin    = 40,
+               .right_margin   = 40,
+               .upper_margin   = 10,
+               .lower_margin   = 10,
+               .hsync_len      = 32,
+               .vsync_len      = 5,
                .xres           = 1366,
                .yres           = 768,
        },
        [1] = { /* TV & LCD Connected */
-               .left_margin    = 70,
-               .right_margin   = 70,
-               .upper_margin   = 12,
-               .lower_margin   = 13,
-               .hsync_len      = 5,
-               .vsync_len      = 32,
+               .left_margin    = 83,
+               .right_margin   = 83,
+               .upper_margin   = 34,
+               .lower_margin   = 34,
+               .hsync_len      = 32,
+               .vsync_len      = 5,
                .xres           = 1280,
                .yres           = 720,
        },
@@ -955,7 +955,7 @@ static void __init exynos5250_dt_machine_init(void)
                        smdk5250_lcd1_pdata.panel[i].timing = snow_fb_window[i];
 
                smdk5250_lcd1_pdata.panel_type = DP_LCD;
-               smdk5250_lcd1_pdata.clock_rate = 267 * 1000 * 1000;
+               smdk5250_lcd1_pdata.clock_rate = 70250000;
                smdk5250_lcd1_pdata.vidcon1 = 0;
 #endif